Alliance Memory SDRAM 128 MB Surface, 54-Pin 16 bit TSOP
- RS庫存編號:
- 230-8443
- 製造零件編號:
- AS4C8M16SA-7TCNTR
- 製造商:
- Alliance Memory
此圖片僅供參考，請參閲產品詳細資訊及規格
可享批量折扣
小計（1 卷，共 1000 件）*
TWD83,500.00
(不含稅)
TWD87,680.00
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2026年5月11日 發貨
**需要更多嗎？**輸入您需要的數量，然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每卷* |
|---|---|---|
| 1000 - 1000 | TWD83.50 | TWD83,500.00 |
| 2000 + | TWD81.00 | TWD81,000.00 |
* 參考價格
- RS庫存編號:
- 230-8443
- 製造零件編號:
- AS4C8M16SA-7TCNTR
- 製造商:
- Alliance Memory
規格
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法例與合規
產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Alliance Memory | |
| Memory Size | 128MB | |
| Product Type | SDRAM | |
| Organisation | 8M x 16 Bit | |
| Data Bus Width | 16bit | |
| Address Bus Width | 121bit | |
| Maximum Clock Frequency | 166MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 5.4ns | |
| Number of Words | 2M | |
| Mount Type | Surface | |
| Package Type | TSOP | |
| Minimum Operating Temperature | 0°C | |
| Pin Count | 54 | |
| Maximum Operating Temperature | 70°C | |
| Series | AS4C8M16SA | |
| Width | 8.1 mm | |
| Height | 1.2mm | |
| Standards/Approvals | No | |
| Length | 22.35mm | |
| Automotive Standard | No | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 3.6V | |
| 選取全部 | ||
|---|---|---|
品牌 Alliance Memory | ||
Memory Size 128MB | ||
Product Type SDRAM | ||
Organisation 8M x 16 Bit | ||
Data Bus Width 16bit | ||
Address Bus Width 121bit | ||
Maximum Clock Frequency 166MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 5.4ns | ||
Number of Words 2M | ||
Mount Type Surface | ||
Package Type TSOP | ||
Minimum Operating Temperature 0°C | ||
Pin Count 54 | ||
Maximum Operating Temperature 70°C | ||
Series AS4C8M16SA | ||
Width 8.1 mm | ||
Height 1.2mm | ||
Standards/Approvals No | ||
Length 22.35mm | ||
Automotive Standard No | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 3.6V | ||
The Alliance Memory 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL
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