Alliance Memory AS4C8M16SA-7TCN, SDRAM 128Mbit Surface Mount, 166MHz, 3 V to 3.6 V, 54-Pin TSOP
- RS庫存編號:
- 230-8440
- 製造零件編號:
- AS4C8M16SA-7TCN
- 製造商:
- Alliance Memory
可享批量折扣
小計(1 托盤,共 108 件)*
TWD8,985.60
(不含稅)
TWD9,434.88
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2026年4月01日 發貨
**需要更多嗎?**輸入您需要的數量,然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每托盤* |
|---|---|---|
| 108 - 216 | TWD83.20 | TWD8,985.60 |
| 324 - 432 | TWD81.10 | TWD8,758.80 |
| 540 + | TWD79.50 | TWD8,586.00 |
* 參考價格
- RS庫存編號:
- 230-8440
- 製造零件編號:
- AS4C8M16SA-7TCN
- 製造商:
- Alliance Memory
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Alliance Memory | |
| Memory Size | 128Mbit | |
| Organisation | 8M x 16 | |
| SDRAM Class | DDR | |
| Data Rate | 166MHz | |
| Data Bus Width | 16bit | |
| Address Bus Width | 12bit | |
| Number of Bits per Word | 16bit | |
| Maximum Random Access Time | 5.4ns | |
| Number of Words | 8 M | |
| Mounting Type | Surface Mount | |
| Package Type | TSOP | |
| Pin Count | 54 | |
| Dimensions | 22.35 x 10.29 x 1.2mm | |
| Height | 1.2mm | |
| Length | 22.35mm | |
| Minimum Operating Temperature | 0 °C | |
| Maximum Operating Supply Voltage | 3.6 V | |
| Maximum Operating Temperature | +70 °C | |
| Minimum Operating Supply Voltage | 3 V | |
| Width | 10.29mm | |
| 選取全部 | ||
|---|---|---|
品牌 Alliance Memory | ||
Memory Size 128Mbit | ||
Organisation 8M x 16 | ||
SDRAM Class DDR | ||
Data Rate 166MHz | ||
Data Bus Width 16bit | ||
Address Bus Width 12bit | ||
Number of Bits per Word 16bit | ||
Maximum Random Access Time 5.4ns | ||
Number of Words 8 M | ||
Mounting Type Surface Mount | ||
Package Type TSOP | ||
Pin Count 54 | ||
Dimensions 22.35 x 10.29 x 1.2mm | ||
Height 1.2mm | ||
Length 22.35mm | ||
Minimum Operating Temperature 0 °C | ||
Maximum Operating Supply Voltage 3.6 V | ||
Maximum Operating Temperature +70 °C | ||
Minimum Operating Supply Voltage 3 V | ||
Width 10.29mm | ||
The Alliance Memory 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
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