Vishay Isolated TrenchFET 2 Type P, Type N-Channel MOSFET, 700 mA, 20 V Enhancement, 6-Pin SC-70-6 SI1553CDL-T1-GE3
- RS庫存編號:
- 165-6904
- 製造零件編號:
- SI1553CDL-T1-GE3
- 製造商:
- Vishay
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可享批量折扣
查看批量定價選項小計（1 卷，共 3000 件）*
TWD16,800.00
(不含稅)
TWD17,640.00
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2027年3月01日 發貨
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單位 | 每單位 | 每卷* |
|---|---|---|
| 3000 - 12000 | TWD5.60 | TWD16,800.00 |
| 15000 + | TWD5.40 | TWD16,200.00 |
* 參考價格
- RS庫存編號:
- 165-6904
- 製造零件編號:
- SI1553CDL-T1-GE3
- 製造商:
- Vishay
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Vishay | |
| Product Type | MOSFET | |
| Channel Type | Type P, Type N | |
| Maximum Continuous Drain Current Id | 700mA | |
| Maximum Drain Source Voltage Vds | 20V | |
| Package Type | SC-70-6 | |
| Series | TrenchFET | |
| Mount Type | Surface | |
| Pin Count | 6 | |
| Maximum Drain Source Resistance Rds | 1.48mΩ | |
| Channel Mode | Enhancement | |
| Typical Gate Charge Qg @ Vgs | 1.2nC | |
| Maximum Power Dissipation Pd | 340mW | |
| Minimum Operating Temperature | -55°C | |
| Maximum Gate Source Voltage Vgs | 12, -12V | |
| Maximum Operating Temperature | 150°C | |
| Transistor Configuration | Isolated | |
| Width | 1.35mm | |
| Height | 1mm | |
| Length | 2.2mm | |
| Standards/Approvals | No | |
| Number of Elements per Chip | 2 | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Vishay | ||
Product Type MOSFET | ||
Channel Type Type P, Type N | ||
Maximum Continuous Drain Current Id 700mA | ||
Maximum Drain Source Voltage Vds 20V | ||
Package Type SC-70-6 | ||
Series TrenchFET | ||
Mount Type Surface | ||
Pin Count 6 | ||
Maximum Drain Source Resistance Rds 1.48mΩ | ||
Channel Mode Enhancement | ||
Typical Gate Charge Qg @ Vgs 1.2nC | ||
Maximum Power Dissipation Pd 340mW | ||
Minimum Operating Temperature -55°C | ||
Maximum Gate Source Voltage Vgs 12, -12V | ||
Maximum Operating Temperature 150°C | ||
Transistor Configuration Isolated | ||
Width 1.35mm | ||
Height 1mm | ||
Length 2.2mm | ||
Standards/Approvals No | ||
Number of Elements per Chip 2 | ||
Automotive Standard No | ||
- COO (Country of Origin):
- PH
Vishay TrenchFET Series MOSFET, 20V Maximum Drain Source Voltage, 700mA Maximum Continuous Drain Current - SI1553CDL-T1-GE3
This MOSFET is a compact dual-channel surface-mount transistor designed for switching and analogue tasks in small-outline assemblies. It integrates both P-channel and N-channel devices on a single chip, enabling complementary switching topologies and simplified footprint requirements for designers working with low-voltage power rails and signal-level switching.
Features and Benefits:
• Very low Rds(on) of 1.48mΩ for reduced conduction losses
• Typical gate charge Qg of 1.2nC for faster gate-drive response
• Continuous drain current rating of 700mA for moderate-load switching
• Maximum Vds of 20V to support low-voltage power domains
• Power dissipation capability of 340mW to manage thermal loads
• Typical gate charge Qg of 1.2nC for faster gate-drive response
• Continuous drain current rating of 700mA for moderate-load switching
• Maximum Vds of 20V to support low-voltage power domains
• Power dissipation capability of 340mW to manage thermal loads
Applications
• Suitable for battery management and power-distribution circuits
• Ideal for load switching in portable instrumentation
• Used with level-shifting and complementary FET stages
• Can be used for low-voltage motor-control driver stages
• Ideal for load switching in portable instrumentation
• Used with level-shifting and complementary FET stages
• Can be used for low-voltage motor-control driver stages
What package style does it use and how many pins are present?
It comes in a six-pin SC-70 SMD package which conserves board area while providing separate terminals for dual devices.
What gate voltage limits should the design respect?
Gate-to-source voltage must be contained within ±12V to prevent device stress and ensure safe operation.
What operating temperature range can be expected in deployment?
It tolerates a wide ambient span from -55°C up to 150°C, supporting demanding thermal environments.
Does the device include multiple elements per die and how does that affect layout?
The chip houses two discrete elements, enabling mirrored routing for complementary circuits and reducing component count.
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