Digilent 410-376 Xilinx Spartan-7 Development Board
- RS庫存編號:
- 184-0485
- 製造零件編號:
- 410-376
- 製造商:
- Digilent
可享批量折扣
小計（1 件）*
TWD3,559.00
(不含稅)
TWD3,736.95
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 7 件從 2025年12月26日 起裝運發貨
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單位 | 每單位 |
|---|---|
| 1 - 4 | TWD3,559.00 |
| 5 + | TWD3,452.00 |
* 參考價格
- RS庫存編號:
- 184-0485
- 製造零件編號:
- 410-376
- 製造商:
- Digilent
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Digilent | |
| Programmable Logic Technology | FPGA | |
| Kit Classification | Development Board | |
| Kit Name | Xilinx Spartan-7 | |
| 選取全部 | ||
|---|---|---|
品牌 Digilent | ||
Programmable Logic Technology FPGA | ||
Kit Classification Development Board | ||
Kit Name Xilinx Spartan-7 | ||
Xilinx Spartan-7 FPGA (XC7S25-1CSGA225C)
3,650 slices containing four 6-input LUTs and 8 flip-flops
1,620 Kbits of fast block RAM
Three clock management tile, each with a phase-locked loop and mixed-mode clock manager
80 DSP slices
Internal clock speeds exceeding 450 MHz
On-chip analogue-to-digital converter (XADC)
Programmable over JTAG and Quad-SPI Flash
Memory
4 MB Quad-SPI Flash
Power
Powered from USB or 5V external supply connected to DIP pin 24 (micro USB cable NOT included)
USB
USB-JTAG programming circuitry
USB-UART bridge
Push-buttons and LEDs
2 Buttons
4 LEDs
1 RGB LED
Expansion Connectors
1 Pmod connector
8 total FPGA I/O
48-pin DIP form-factor headers
36 populated pins
32 total FPGA I/O
2 Single-ended 0-3.3V analogue inputs to XADC
3,650 slices containing four 6-input LUTs and 8 flip-flops
1,620 Kbits of fast block RAM
Three clock management tile, each with a phase-locked loop and mixed-mode clock manager
80 DSP slices
Internal clock speeds exceeding 450 MHz
On-chip analogue-to-digital converter (XADC)
Programmable over JTAG and Quad-SPI Flash
Memory
4 MB Quad-SPI Flash
Power
Powered from USB or 5V external supply connected to DIP pin 24 (micro USB cable NOT included)
USB
USB-JTAG programming circuitry
USB-UART bridge
Push-buttons and LEDs
2 Buttons
4 LEDs
1 RGB LED
Expansion Connectors
1 Pmod connector
8 total FPGA I/O
48-pin DIP form-factor headers
36 populated pins
32 total FPGA I/O
2 Single-ended 0-3.3V analogue inputs to XADC
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