可享批量折扣
查看批量定價選項小計（1 卷，共 1000 件）*
TWD181,500.00
(不含稅)
TWD190,580.00
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2026年12月09日 發貨
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單位 | 每單位 | 每卷* |
|---|---|---|
| 1000 - 4000 | TWD181.50 | TWD181,500.00 |
| 5000 + | TWD176.10 | TWD176,100.00 |
* 參考價格
- RS庫存編號:
- 181-7442
- 製造零件編號:
- CY62148ELL-55SXIT
- 製造商:
- Infineon
規格
產品概覽和技術數據資料表
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產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Infineon | |
| Memory Size | 4MB | |
| Product Type | SRAM | |
| Organisation | 512 k x 8 Bit | |
| Number of Words | 512K | |
| Number of Bits per Word | 8 | |
| Maximum Random Access Time | 45ns | |
| Address Bus Width | 8bit | |
| Maximum Clock Frequency | 1MHz | |
| Timing Type | Asynchronous | |
| Minimum Supply Voltage | 4.5V | |
| Mount Type | Surface | |
| Maximum Supply Voltage | 5.5V | |
| Minimum Operating Temperature | -40°C | |
| Package Type | SOIC | |
| Maximum Operating Temperature | 85°C | |
| Pin Count | 32 | |
| Series | CY62148E | |
| Length | 20.75mm | |
| Height | 2.81mm | |
| Width | 11.43mm | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Supply Current | 20mA | |
| 選取全部 | ||
|---|---|---|
品牌 Infineon | ||
Memory Size 4MB | ||
Product Type SRAM | ||
Organisation 512 k x 8 Bit | ||
Number of Words 512K | ||
Number of Bits per Word 8 | ||
Maximum Random Access Time 45ns | ||
Address Bus Width 8bit | ||
Maximum Clock Frequency 1MHz | ||
Timing Type Asynchronous | ||
Minimum Supply Voltage 4.5V | ||
Mount Type Surface | ||
Maximum Supply Voltage 5.5V | ||
Minimum Operating Temperature -40°C | ||
Package Type SOIC | ||
Maximum Operating Temperature 85°C | ||
Pin Count 32 | ||
Series CY62148E | ||
Length 20.75mm | ||
Height 2.81mm | ||
Width 11.43mm | ||
Standards/Approvals No | ||
Automotive Standard No | ||
Supply Current 20mA | ||
Infineon CY62148E Series SRAM, 4MB Memory Size, 1MHz Maximum Clock Frequency - CY62148ELL-55SXIT
This SRAM is a static memory device designed for fast, low-latency data storage in embedded systems. It operates within a standard single-supply digital environment and is intended for surface-mount installation on printed circuit assemblies. The component supports asynchronous read/write interaction and is suitable for applications requiring moderate capacity and deterministic access timing.
Features and Benefits:
• 45ns random access time improves deterministic data retrieval
• 1MHz maximum clock frequency reduces power during polling
• 4MB organisation delivers sizeable volatile storage capacity
• 4.5V-5.5V supply range allows standard 5V system compatibility
• 20mA typical supply current lowers energy use in idle states
• 32-pin SOIC package supports compact board layouts
• 1MHz maximum clock frequency reduces power during polling
• 4MB organisation delivers sizeable volatile storage capacity
• 4.5V-5.5V supply range allows standard 5V system compatibility
• 20mA typical supply current lowers energy use in idle states
• 32-pin SOIC package supports compact board layouts
Applications
• Suitable for buffering in industrial control units
• Ideal for data logging in instrumentation systems
• Used with microcontrollers for code shadowing
• Can be used for frame buffering in legacy video electronics
• Suitable for temporary storage in communication gateways
• Ideal for data logging in instrumentation systems
• Used with microcontrollers for code shadowing
• Can be used for frame buffering in legacy video electronics
• Suitable for temporary storage in communication gateways
What temperature extremes can it withstand in operation?
It is rated to operate from -40°C up to 85°C for use in demanding ambient conditions.
How is the memory organised internally for addressing?
The device presents 512K words of 8-bit width accessed via an 8-bit address interface.
Which physical footprint and mounting method does it require?
The component is supplied in a 32-pin SOIC package for surface-mount placement measuring 20.75mm length and 11.43mm width.
What are the primary electrical constraints to consider in designs?
Designers should observe the 5.5V maximum supply and ensure timing meets the 45 ns access requirement while accounting for the asynchronous timing scheme.