Alliance Memory AS4C32M16SB-7TIN SDRAM 512 MB Surface, 54-Pin 16 bit TSOP
- RS庫存編號:
- 230-8428
- Distrelec 貨號:
- 301-51-413
- 製造零件編號:
- AS4C32M16SB-7TIN
- 製造商:
- Alliance Memory
可享批量折扣
小計（1 件）*
TWD496.00
(不含稅)
TWD520.80
(含稅)
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單位 | 每單位 |
|---|---|
| 1 - 9 | TWD496.00 |
| 10 - 24 | TWD483.00 |
| 25 - 49 | TWD470.00 |
| 50 - 74 | TWD459.00 |
| 75 + | TWD448.00 |
* 參考價格
- RS庫存編號:
- 230-8428
- Distrelec 貨號:
- 301-51-413
- 製造零件編號:
- AS4C32M16SB-7TIN
- 製造商:
- Alliance Memory
規格
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Alliance Memory | |
| Memory Size | 512MB | |
| Product Type | SDRAM | |
| Organisation | 32M x 16 Bit | |
| Data Bus Width | 16bit | |
| Address Bus Width | 13bit | |
| Maximum Clock Frequency | 166MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 5.4ns | |
| Number of Words | 8K | |
| Mount Type | Surface | |
| Package Type | TSOP | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 54 | |
| Maximum Operating Temperature | 85°C | |
| Width | 10.29 mm | |
| Length | 22.35mm | |
| Height | 1.2mm | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Supply Voltage | 3V | |
| 選取全部 | ||
|---|---|---|
品牌 Alliance Memory | ||
Memory Size 512MB | ||
Product Type SDRAM | ||
Organisation 32M x 16 Bit | ||
Data Bus Width 16bit | ||
Address Bus Width 13bit | ||
Maximum Clock Frequency 166MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 5.4ns | ||
Number of Words 8K | ||
Mount Type Surface | ||
Package Type TSOP | ||
Minimum Operating Temperature -40°C | ||
Pin Count 54 | ||
Maximum Operating Temperature 85°C | ||
Width 10.29 mm | ||
Length 22.35mm | ||
Height 1.2mm | ||
Standards/Approvals No | ||
Automotive Standard No | ||
Maximum Supply Voltage 3.6V | ||
Minimum Supply Voltage 3V | ||
The Alliance Memory 512Mb SDRAM is a high-speed CMOS synchronous DRAM containing 512 Mbits. It is internally configured as 4 Banks of 8M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a Bank Activate command which is then followed by a Read or Write command.
Auto Refresh and Self Refresh
8192 refresh cycles/64ms
CKE power down mode
Single +3.3V ±0.3V power supply
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