Alliance Memory AS4C16M16SA-6TIN SDRAM 256 MB Surface, 54-Pin 16 bit TSOP
- RS庫存編號:
- 230-8416
- Distrelec 貨號:
- 304-31-276
- 製造零件編號:
- AS4C16M16SA-6TIN
- 製造商:
- Alliance Memory
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TWD240.00
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TWD252.00
(含稅)
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|---|---|---|
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* 參考價格
- RS庫存編號:
- 230-8416
- Distrelec 貨號:
- 304-31-276
- 製造零件編號:
- AS4C16M16SA-6TIN
- 製造商:
- Alliance Memory
規格
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產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Alliance Memory | |
| Product Type | SDRAM | |
| Memory Size | 256MB | |
| Organisation | 16M x 16 Bit | |
| Data Bus Width | 16bit | |
| Address Bus Width | 13bit | |
| Maximum Clock Frequency | 166MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 5ns | |
| Number of Words | 4M | |
| Mount Type | Surface | |
| Package Type | TSOP | |
| Pin Count | 54 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Length | 22.35mm | |
| Series | AS4C16M16SA-C&I | |
| Standards/Approvals | No | |
| Width | 10.29 mm | |
| Height | 1.2mm | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Supply Voltage | 3V | |
| Supply Current | 60mA | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Alliance Memory | ||
Product Type SDRAM | ||
Memory Size 256MB | ||
Organisation 16M x 16 Bit | ||
Data Bus Width 16bit | ||
Address Bus Width 13bit | ||
Maximum Clock Frequency 166MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 5ns | ||
Number of Words 4M | ||
Mount Type Surface | ||
Package Type TSOP | ||
Pin Count 54 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Length 22.35mm | ||
Series AS4C16M16SA-C&I | ||
Standards/Approvals No | ||
Width 10.29 mm | ||
Height 1.2mm | ||
Maximum Supply Voltage 3.6V | ||
Minimum Supply Voltage 3V | ||
Supply Current 60mA | ||
Automotive Standard No | ||
The Alliance Memory 256Mb SDRAM is a high-speed CMOS synchronous DRAM containing 256 Mbits. It is internally configured as 4 Banks of 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
Fast access time from clock: 5/5.4 ns
Fast clock rate: 166/143 MHz
Fully synchronous operation
Internal pipelined architecture
4M word x 16-bit x 4-bank
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