Alliance Memory AS4C128M16D2A-25BCN SDRAM 2 GB Surface, 84-Pin 16 bit FBGA
- RS庫存編號:
- 230-8410
- Distrelec 貨號:
- 301-51-367
- 製造零件編號:
- AS4C128M16D2A-25BCN
- 製造商:
- Alliance Memory
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- RS庫存編號:
- 230-8410
- Distrelec 貨號:
- 301-51-367
- 製造零件編號:
- AS4C128M16D2A-25BCN
- 製造商:
- Alliance Memory
規格
產品概覽和技術數據資料表
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Alliance Memory | |
| Memory Size | 2GB | |
| Product Type | SDRAM | |
| Organisation | 128M x 16 | |
| Data Bus Width | 16bit | |
| Address Bus Width | 13bit | |
| Maximum Clock Frequency | 400MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 12.5ns | |
| Mount Type | Surface | |
| Package Type | FBGA | |
| Minimum Operating Temperature | 0°C | |
| Pin Count | 84 | |
| Maximum Operating Temperature | 85°C | |
| Series | AS4C128M16D2A | |
| Standards/Approvals | RoHS | |
| Length | 8.1mm | |
| Height | 1.2mm | |
| Width | 12.5 mm | |
| Minimum Supply Voltage | 1.7V | |
| Automotive Standard | No | |
| Maximum Supply Voltage | 1.9V | |
| 選取全部 | ||
|---|---|---|
品牌 Alliance Memory | ||
Memory Size 2GB | ||
Product Type SDRAM | ||
Organisation 128M x 16 | ||
Data Bus Width 16bit | ||
Address Bus Width 13bit | ||
Maximum Clock Frequency 400MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 12.5ns | ||
Mount Type Surface | ||
Package Type FBGA | ||
Minimum Operating Temperature 0°C | ||
Pin Count 84 | ||
Maximum Operating Temperature 85°C | ||
Series AS4C128M16D2A | ||
Standards/Approvals RoHS | ||
Length 8.1mm | ||
Height 1.2mm | ||
Width 12.5 mm | ||
Minimum Supply Voltage 1.7V | ||
Automotive Standard No | ||
Maximum Supply Voltage 1.9V | ||
The Alliance Memory 2Gb DDR2 is a high-speed CMOS Double-Data- Rate-Two (DDR2), synchronous dynamic random - access memory (SDRAM) containing 2048 Mbits in a 16- bit wide data I/Os. It is internally configured as a 8-bank DRAM, 8 banks x 16Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) impedance adjustment, and On Die Termination(ODT).
8 internal banks for concurrent operation
4-bit prefetch architecture
Internal pipeline architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
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