Alliance Memory AS4C128M16D2A-25BCN, SDRAM 2Gbit Surface Mount, 400MHz, 1.7 V to 1.9 V, 84-Pin FBGA
- RS庫存編號:
- 230-8409
- 製造零件編號:
- AS4C128M16D2A-25BCN
- 製造商:
- Alliance Memory
可享批量折扣
小計(1 托盤,共 209 件)*
TWD72,376.70
(不含稅)
TWD75,996.58
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2026年4月17日 發貨
**需要更多嗎?**輸入您需要的數量,然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每托盤* |
|---|---|---|
| 209 - 209 | TWD346.30 | TWD72,376.70 |
| 418 + | TWD335.90 | TWD70,203.10 |
* 參考價格
- RS庫存編號:
- 230-8409
- 製造零件編號:
- AS4C128M16D2A-25BCN
- 製造商:
- Alliance Memory
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Alliance Memory | |
| Memory Size | 2Gbit | |
| Organisation | 128M x 16 | |
| SDRAM Class | DDR2 | |
| Data Rate | 400MHz | |
| Data Bus Width | 16bit | |
| Address Bus Width | 13bit | |
| Number of Bits per Word | 16bit | |
| Maximum Random Access Time | 12.5ns | |
| Number of Words | 128 M | |
| Mounting Type | Surface Mount | |
| Package Type | FBGA | |
| Pin Count | 84 | |
| Dimensions | 8.1 x 12.5 x 1.2mm | |
| Height | 1.2mm | |
| Length | 8.1mm | |
| Minimum Operating Temperature | 0 °C | |
| Minimum Operating Supply Voltage | 1.7 V | |
| Maximum Operating Temperature | +85 °C | |
| Maximum Operating Supply Voltage | 1.9 V | |
| Width | 12.5mm | |
| 選取全部 | ||
|---|---|---|
品牌 Alliance Memory | ||
Memory Size 2Gbit | ||
Organisation 128M x 16 | ||
SDRAM Class DDR2 | ||
Data Rate 400MHz | ||
Data Bus Width 16bit | ||
Address Bus Width 13bit | ||
Number of Bits per Word 16bit | ||
Maximum Random Access Time 12.5ns | ||
Number of Words 128 M | ||
Mounting Type Surface Mount | ||
Package Type FBGA | ||
Pin Count 84 | ||
Dimensions 8.1 x 12.5 x 1.2mm | ||
Height 1.2mm | ||
Length 8.1mm | ||
Minimum Operating Temperature 0 °C | ||
Minimum Operating Supply Voltage 1.7 V | ||
Maximum Operating Temperature +85 °C | ||
Maximum Operating Supply Voltage 1.9 V | ||
Width 12.5mm | ||
The Alliance Memory 2Gb DDR2 is a high-speed CMOS Double-Data- Rate-Two (DDR2), synchronous dynamic random - access memory (SDRAM) containing 2048 Mbits in a 16- bit wide data I/Os. It is internally configured as a 8-bank DRAM, 8 banks x 16Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) impedance adjustment, and On Die Termination(ODT).
8 internal banks for concurrent operation
4-bit prefetch architecture
Internal pipeline architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
4-bit prefetch architecture
Internal pipeline architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
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