Alliance Memory AS4C1G8D4A-62BIN SDRAM 1 GB Surface, 78-Pin 8 bit FBGA
- RS庫存編號:
- 665-384
- 製造零件編號:
- AS4C1G8D4A-62BIN
- 製造商:
- Alliance Memory
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TWD819.00
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TWD859.95
(含稅)
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單位 | 每單位 |
|---|---|
| 1 + | TWD819.00 |
* 參考價格
- RS庫存編號:
- 665-384
- 製造零件編號:
- AS4C1G8D4A-62BIN
- 製造商:
- Alliance Memory
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Alliance Memory | |
| Product Type | SDRAM | |
| Memory Size | 1GB | |
| Organisation | 1G x 8 | |
| Data Bus Width | 8bit | |
| Number of Bits per Word | 8 | |
| Maximum Clock Frequency | 1600MHz | |
| Mount Type | Surface | |
| Package Type | FBGA | |
| Pin Count | 78 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 95°C | |
| Height | 1.2mm | |
| Standards/Approvals | JEDEC, RoHS | |
| Width | 7.5 mm | |
| Length | 12mm | |
| Maximum Supply Voltage | 1.26V | |
| Minimum Supply Voltage | 1.14V | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Alliance Memory | ||
Product Type SDRAM | ||
Memory Size 1GB | ||
Organisation 1G x 8 | ||
Data Bus Width 8bit | ||
Number of Bits per Word 8 | ||
Maximum Clock Frequency 1600MHz | ||
Mount Type Surface | ||
Package Type FBGA | ||
Pin Count 78 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 95°C | ||
Height 1.2mm | ||
Standards/Approvals JEDEC, RoHS | ||
Width 7.5 mm | ||
Length 12mm | ||
Maximum Supply Voltage 1.26V | ||
Minimum Supply Voltage 1.14V | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Alliance Memory 8Gb DDR4 DRAM in a 78-ball FBGA package supports JEDEC clock jitter specifications and features a bidirectional differential data strobe along with differential clocks. It is internally organized into 16 banks, grouped as four sets of four banks each, with separated I/O gating structures by bank group. The device uses an 8n-bit prefect architecture and supports power-saving features such as precharge and active power-down, auto refresh, self refresh, low-power auto self refresh (LPASR), self refresh abort, and fine granularity refresh, ensuring efficient and high-performance operation.
Internal VREFDQ Training
Read Preamble Training
Control Gear Down Mode
Per DRAM Addressability
Output Driver Impedance Control
Dynamic on-die termination
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