Renesas Electronics 9DB106BGLF Clock Buffer 28-Pin TSSOP
- RS庫存編號:
- 263-7981
- 製造零件編號:
- 9DB106BGLF
- 製造商:
- Renesas Electronics
可享批量折扣
小計（1 包，共 2 件）*
TWD295.00
(不含稅)
TWD309.76
(含稅)
訂單超過 $1,300.00 免費送貨
有庫存
- 加上 130 件從 2026年1月05日 起發貨
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單位 | 每單位 | 每包* |
|---|---|---|
| 2 - 8 | TWD147.50 | TWD295.00 |
| 10 - 18 | TWD132.00 | TWD264.00 |
| 20 - 48 | TWD129.50 | TWD259.00 |
| 50 - 98 | TWD125.00 | TWD250.00 |
| 100 + | TWD108.50 | TWD217.00 |
* 參考價格
- RS庫存編號:
- 263-7981
- 製造零件編號:
- 9DB106BGLF
- 製造商:
- Renesas Electronics
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Renesas Electronics | |
| Number of Elements per Chip | 5 | |
| Maximum Supply Current | 5 μA | |
| Maximum Input Frequency | 105MHz | |
| Mounting Type | SMD | |
| Package Type | TSSOP | |
| Pin Count | 28 | |
| 選取全部 | ||
|---|---|---|
品牌 Renesas Electronics | ||
Number of Elements per Chip 5 | ||
Maximum Supply Current 5 μA | ||
Maximum Input Frequency 105MHz | ||
Mounting Type SMD | ||
Package Type TSSOP | ||
Pin Count 28 | ||
- COO (Country of Origin):
- TW
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.
SMBus Interface
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
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