Renesas Electronics 9DB106BGLF Clock Buffer 28-Pin TSSOP

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小計(1 管,共 50 件)*

TWD5,590.00

(不含稅)

TWD5,869.50

(含稅)

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50 - 50TWD111.80TWD5,590.00
100 - 200TWD109.50TWD5,475.00
250 - 450TWD107.30TWD5,365.00
500 +TWD105.20TWD5,260.00

* 參考價格

RS庫存編號:
263-7980
製造零件編號:
9DB106BGLF
製造商:
Renesas Electronics
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品牌

Renesas Electronics

Number of Elements per Chip

5

Maximum Supply Current

5 μA

Maximum Input Frequency

105MHz

Mounting Type

SMD

Package Type

TSSOP

Pin Count

28

COO (Country of Origin):
TW
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.

SMBus Interface
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps

For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.


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