Nexperia 74HCT595PW-Q100,11 1 Surface Shift Register/Latch 74HCT TSSOP, 16-Pin

The 74HC595-Q100, 74HCT595-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74HC595-Q100, 74HCT595-Q100 are 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks. Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP).

Automotive product qualification in accordance with AEC-Q100 (Grade 1)