Renesas Electronics 8305AGLF Clock Buffer, 16-Pin 4 TSSOP
- RS庫存編號:
- 216-6205
- 製造零件編號:
- 8305AGLF
- 製造商:
- Renesas Electronics
此圖片僅供參考，請參閲產品詳細資訊及規格
可享批量折扣
小計（1 管，共 96 件）*
TWD16,128.00
(不含稅)
TWD16,934.40
(含稅)
訂單超過 $1,300.00 免費送貨
最後的 RS 庫存
- 最終 96 個，準備發貨
單位 | 每單位 | 每管* |
|---|---|---|
| 96 - 96 | TWD168.00 | TWD16,128.00 |
| 192 - 288 | TWD164.60 | TWD15,801.60 |
| 384 + | TWD161.30 | TWD15,484.80 |
* 參考價格
- RS庫存編號:
- 216-6205
- 製造零件編號:
- 8305AGLF
- 製造商:
- Renesas Electronics
規格
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法例與合規
產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Minimum Supply Voltage | 1.5V | |
| Pin Count | 16 | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Length | 4mm | |
| Standards/Approvals | No | |
| Width | 3.3 mm | |
| Series | 8305A | |
| Height | 0.9mm | |
| Automotive Standard | No | |
| Number of Outputs | 4 | |
| 選取全部 | ||
|---|---|---|
品牌 Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Minimum Supply Voltage 1.5V | ||
Pin Count 16 | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Length 4mm | ||
Standards/Approvals No | ||
Width 3.3 mm | ||
Series 8305A | ||
Height 0.9mm | ||
Automotive Standard No | ||
Number of Outputs 4 | ||
The Renesas Electronics ICS8305 is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer. The ICS8305 has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.
Four LVCMOS / LVTTL outputs, 7 output impedance
Selectable differential or LVCMOS / LVTTL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
Maximum output frequency: 350MHz
Output skew: 35ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)