Renesas Electronics 8T49N242-999NLGI Clock Buffer 40-Pin VFQFN
- RS庫存編號:
- 250-3483
- 製造零件編號:
- 8T49N242-999NLGI
- 製造商:
- Renesas Electronics
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TWD235.00
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TWD246.75
(含稅)
添加 6 件 件可免費送貨
最後的 RS 庫存
- 最終 490 個，準備發貨
單位 | 每單位 |
|---|---|
| 1 - 9 | TWD235.00 |
| 10 - 24 | TWD231.00 |
| 25 - 49 | TWD225.00 |
| 50 - 99 | TWD221.00 |
| 100 + | TWD217.00 |
* 參考價格
- RS庫存編號:
- 250-3483
- 製造零件編號:
- 8T49N242-999NLGI
- 製造商:
- Renesas Electronics
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 875MHz | |
| Mount Type | Surface | |
| Package Type | VFQFN | |
| Pin Count | 40 | |
| Number of Outputs | 9 | |
| Minimum Supply Voltage | 3.14V | |
| Maximum Supply Voltage | 3.47V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | RoHS | |
| Height | 1mm | |
| Length | 6mm | |
| Width | 6 mm | |
| Series | 8T49N242 | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 875MHz | ||
Mount Type Surface | ||
Package Type VFQFN | ||
Pin Count 40 | ||
Number of Outputs 9 | ||
Minimum Supply Voltage 3.14V | ||
Maximum Supply Voltage 3.47V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals RoHS | ||
Height 1mm | ||
Length 6mm | ||
Width 6 mm | ||
Series 8T49N242 | ||
Automotive Standard No | ||
The Renesas Electronics frequency translator has one fractional-feedback PLL that can be used as a jitter attenuator and frequency translator. It is equipped with four integer output dividers, allowing the generation of up to four different output frequencies, ranging from 8kHz to 1GHz. These frequencies are completely independent of the input reference frequencies, and the crystal reference frequency. The outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels.
It accepts up to two differential or single-ended input clocks and a fundamental-mode crystal input
The internal PLL can lock to either of the input reference clocks or just to the crystal to behave as a frequency synthesizer
The device supports hitless reference switching between input clocks
The device monitors both input clocks for Loss of Signal and generates an alarm when an input clock failure is detected
The PLL has a register-selectable loop bandwidth from 0.2Hz to 6.4kHz
The device is programmable through an I2C interface
It also supports I2C master capability to allow the register configuration to be read from an external EEPROM
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