Renesas Electronics 8P34S1208NBGI Clock Buffer 28-Pin VFQFPN
- RS庫存編號:
- 235-8706
- 製造零件編號:
- 8P34S1208NBGI
- 製造商:
- Renesas Electronics
此圖片僅供參考，請參閲產品詳細資訊及規格
可享批量折扣
小計（1 托盤，共 490 件）*
TWD132,594.00
(不含稅)
TWD139,223.70
(含稅)
訂單超過 $1,300.00 免費送貨
有庫存
- 490 件準備從其他地點送貨
**需要更多嗎？**輸入您需要的數量，然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每托盤* |
|---|---|---|
| 490 - 490 | TWD270.60 | TWD132,594.00 |
| 980 + | TWD265.20 | TWD129,948.00 |
* 參考價格
- RS庫存編號:
- 235-8706
- 製造零件編號:
- 8P34S1208NBGI
- 製造商:
- Renesas Electronics
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 1.2GHz | |
| Maximum Propagation Delay Time | 250ps | |
| Mount Type | Surface | |
| Package Type | VFQFPN | |
| Pin Count | 28 | |
| Number of Outputs | 5 | |
| Minimum Supply Voltage | 1.71V | |
| Maximum Supply Voltage | 1.89V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Width | 5 mm | |
| Length | 5mm | |
| Height | 0.8mm | |
| Standards/Approvals | No | |
| Series | 8P | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 1.2GHz | ||
Maximum Propagation Delay Time 250ps | ||
Mount Type Surface | ||
Package Type VFQFPN | ||
Pin Count 28 | ||
Number of Outputs 5 | ||
Minimum Supply Voltage 1.71V | ||
Maximum Supply Voltage 1.89V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Width 5 mm | ||
Length 5mm | ||
Height 0.8mm | ||
Standards/Approvals No | ||
Series 8P | ||
Automotive Standard No | ||
The Renesas Electronics characterized to operate from a 1.8V or 2.5V power supply. Guaranteed output to output and part to part skew characteristics make the Ideal for those clock distribution applications demanding well defined performance and repeatability. Two selectable differential inputs and eight low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
Two selectable, differential clock input pairs
Has differential input levels like lvds, cml
Maximum input clock frequency is of 1.5 GHz
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