Nexperia 74HCT373D,653 Octal D Type Latch, 8-Bit Non-Inverting, 20-Pin SO
- RS庫存編號:
- 170-5429
- 製造零件編號:
- 74HCT373D,653
- 製造商:
- Nexperia
可享批量折扣
查看批量定價選項小計(1 包,共 25 件)*
TWD250.00
(不含稅)
TWD262.50
(含稅)
訂單超過 $1,300.00 免費送貨
有庫存
- 25 件準備從其他地點送貨
- 加上 1,900 件從 2026年10月08日 起發貨
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單位 | 每單位 | 每包* |
|---|---|---|
| 25 - 475 | TWD10.00 | TWD250.00 |
| 500 - 975 | TWD9.80 | TWD245.00 |
| 1000 + | TWD9.60 | TWD240.00 |
* 參考價格
- RS庫存編號:
- 170-5429
- 製造零件編號:
- 74HCT373D,653
- 製造商:
- Nexperia
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Nexperia | |
| Product Type | Octal D Type Latch | |
| Logic Family | 74HCT | |
| Logic Function | D Type | |
| Number of Channels | 8 | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Package Type | SO | |
| Pin Count | 20 | |
| Minimum Supply Voltage | 4.5V | |
| Maximum Supply Voltage | 5.5V | |
| Input Level | TTL | |
| Minimum Operating Temperature | -40°C | |
| Maximum Propagation Delay Time @ CL | 45ns | |
| Maximum Operating Temperature | 125°C | |
| Length | 13mm | |
| Series | 74HCT | |
| Height | 2.45mm | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Output Type | 3 State | |
| 選取全部 | ||
|---|---|---|
品牌 Nexperia | ||
Product Type Octal D Type Latch | ||
Logic Family 74HCT | ||
Logic Function D Type | ||
Number of Channels 8 | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Package Type SO | ||
Pin Count 20 | ||
Minimum Supply Voltage 4.5V | ||
Maximum Supply Voltage 5.5V | ||
Input Level TTL | ||
Minimum Operating Temperature -40°C | ||
Maximum Propagation Delay Time @ CL 45ns | ||
Maximum Operating Temperature 125°C | ||
Length 13mm | ||
Series 74HCT | ||
Height 2.45mm | ||
Standards/Approvals No | ||
Automotive Standard No | ||
Output Type 3 State | ||
- COO (Country of Origin):
- CN
The 74HC373: 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to Interface inputs to voltages in excess of VCC.
Low switch leakage
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