Nexperia Octal D Type Latch, 8-Bit Non-Inverting, 20-Pin SO
- RS庫存編號:
- 170-4869
- 製造零件編號:
- 74HCT373D,653
- 製造商:
- Nexperia
此圖片僅供參考，請參閲產品詳細資訊及規格
可享批量折扣
小計（1 卷，共 2000 件）*
TWD17,200.00
(不含稅)
TWD18,060.00
(含稅)
訂單超過 $1,300.00 免費送貨
有庫存
- 2,000 件準備從其他地點送貨
**需要更多嗎？**輸入您需要的數量，然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每卷* |
|---|---|---|
| 2000 - 2000 | TWD8.60 | TWD17,200.00 |
| 4000 + | TWD8.40 | TWD16,800.00 |
* 參考價格
- RS庫存編號:
- 170-4869
- 製造零件編號:
- 74HCT373D,653
- 製造商:
- Nexperia
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Nexperia | |
| Product Type | Octal D Type Latch | |
| Logic Family | 74HCT | |
| Logic Function | D Type | |
| Number of Channels | 8 | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Package Type | SO | |
| Pin Count | 20 | |
| Minimum Supply Voltage | 4.5V | |
| Maximum Supply Voltage | 5.5V | |
| Input Level | TTL | |
| Maximum Propagation Delay Time @ CL | 45ns | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Series | 74HCT | |
| Standards/Approvals | No | |
| Length | 13mm | |
| Height | 2.45mm | |
| Output Type | 3 State | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Nexperia | ||
Product Type Octal D Type Latch | ||
Logic Family 74HCT | ||
Logic Function D Type | ||
Number of Channels 8 | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Package Type SO | ||
Pin Count 20 | ||
Minimum Supply Voltage 4.5V | ||
Maximum Supply Voltage 5.5V | ||
Input Level TTL | ||
Maximum Propagation Delay Time @ CL 45ns | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Series 74HCT | ||
Standards/Approvals No | ||
Length 13mm | ||
Height 2.45mm | ||
Output Type 3 State | ||
Automotive Standard No | ||
- COO (Country of Origin):
- CN
The 74HC373, 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE.
Mixed 5 V and 3.3 V applications
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
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