onsemi MC100EPT25DG, Logic Level Translator Translator 2 ECL to LVTTL, 8-Pin SOIC
- RS庫存編號:
- 186-9227
- 製造零件編號:
- MC100EPT25DG
- 製造商:
- onsemi
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TWD342.00
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TWD359.10
(含稅)
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* 參考價格
- RS庫存編號:
- 186-9227
- 製造零件編號:
- MC100EPT25DG
- 製造商:
- onsemi
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | onsemi | |
| Direction Type | Uni-Directional | |
| Product Type | Logic Level Translator | |
| Logic Family | ECL | |
| Maximum Propagation Delay Time @ CL | 2ns | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Number of Elements per Chip | 2 | |
| Output Type | LVTTL | |
| Pin Count | 8 | |
| Logic Function | Translator | |
| Maximum Low Level Output Current | 24mA | |
| Maximum High Level Output Current | -3mA | |
| Minimum Supply Voltage | 3V | |
| Translation | ECL to LVTTL | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Height | 1.5mm | |
| Length | 5mm | |
| Standards/Approvals | No | |
| Series | MC100EPT2 | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 onsemi | ||
Direction Type Uni-Directional | ||
Product Type Logic Level Translator | ||
Logic Family ECL | ||
Maximum Propagation Delay Time @ CL 2ns | ||
Mount Type Surface | ||
Package Type SOIC | ||
Number of Elements per Chip 2 | ||
Output Type LVTTL | ||
Pin Count 8 | ||
Logic Function Translator | ||
Maximum Low Level Output Current 24mA | ||
Maximum High Level Output Current -3mA | ||
Minimum Supply Voltage 3V | ||
Translation ECL to LVTTL | ||
Maximum Supply Voltage 3.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Height 1.5mm | ||
Length 5mm | ||
Standards/Approvals No | ||
Series MC100EPT2 | ||
Automotive Standard No | ||
The MC100EPT25 is a Differential LVECL/ECL to LVTTL translator. This device requires +3.3V, -3.3V to -5.2V, and ground. The small outline 8-lead SOIC package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal.
The VBB output allows the EPT25 to also be used in a single-ended input mode. In this mode the VBB output is tied to the D input for a inverting buffer or the D input for a non-inverting buffer. If used, the VBB pin should be bypassed to ground with at least a 0.01 μF capacitor.
1.1ns Typical Propagation Delay
Maximum Frequency > 275 MHz Typical
Operating Range: VCC = 3.0 V to 3.6 V, VEE = -5.5 V to -3.0 V, GND = 0 V
24mA TTL outputs
Q Output will default LOW with inputs open or at GND
VBB Output
Open Input Default State
Safety Clamp on Inputs
Pb-Free Packages are Available