Infineon SRAM, CY7C1041G-10ZSXI- 4 MB
- RS庫存編號:
- 273-7349
- 製造零件編號:
- CY7C1041G-10ZSXI
- 製造商:
- Infineon
此圖片僅供參考，請參閲產品詳細資訊及規格
可享批量折扣
小計（1 托盤，共 135 件）*
TWD19,669.50
(不含稅)
TWD20,652.30
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2026年6月16日 發貨
**需要更多嗎？**輸入您需要的數量，然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每托盤* |
|---|---|---|
| 135 - 135 | TWD145.70 | TWD19,669.50 |
| 270 + | TWD141.30 | TWD19,075.50 |
* 參考價格
- RS庫存編號:
- 273-7349
- 製造零件編號:
- CY7C1041G-10ZSXI
- 製造商:
- Infineon
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Infineon | |
| Memory Size | 4MB | |
| Product Type | SRAM | |
| Organisation | 256 K x 16 | |
| Number of Words | 256K | |
| Number of Bits per Word | 16 | |
| Minimum Supply Voltage | 0.5V | |
| Mount Type | Surface | |
| Maximum Supply Voltage | 0.5V | |
| Package Type | TSOP II | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 44 | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | RoHS | |
| Length | 18.51mm | |
| Width | 1.19 mm | |
| Series | CY7C1041G | |
| Height | 10.26mm | |
| Supply Current | 45mA | |
| 選取全部 | ||
|---|---|---|
品牌 Infineon | ||
Memory Size 4MB | ||
Product Type SRAM | ||
Organisation 256 K x 16 | ||
Number of Words 256K | ||
Number of Bits per Word 16 | ||
Minimum Supply Voltage 0.5V | ||
Mount Type Surface | ||
Maximum Supply Voltage 0.5V | ||
Package Type TSOP II | ||
Minimum Operating Temperature -40°C | ||
Pin Count 44 | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals RoHS | ||
Length 18.51mm | ||
Width 1.19 mm | ||
Series CY7C1041G | ||
Height 10.26mm | ||
Supply Current 45mA | ||
The Infineon Static RAM are high performance CMOS fast static RAM device with embedded ECC. This Static RAM device offered in single chip enable option and in multiple pin configurations. This device includes an ERR pin that signals an error detection and correction event during a read cycle. Data writes are performed by asserting the chip enable and write enable inputs LOW, while providing the data on IO 0 through IO 15 and address on A0 through A17 pins. The byte high enable and byte low enable inputs control write operations to the upper and lower bytes of the specified memory location.
High speed
Low active and standby currents
1 bit error detection and correction
TTL compatible inputs and outputs
Embedded ECC for single bit error correction