ISSI IS42S16800F-7TL, SDRAM 128Mbit Surface Mount, 143MHz, 3 V to 3.6 V, 54-Pin TSOP
- RS庫存編號:
- 811-5131P
- 製造零件編號:
- IS42S16800F-7TL
- 製造商:
- ISSI
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- RS庫存編號:
- 811-5131P
- 製造零件編號:
- IS42S16800F-7TL
- 製造商:
- ISSI
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | ISSI | |
| Memory Size | 128Mbit | |
| Organisation | 8M x 16 | |
| Data Rate | 143MHz | |
| Data Bus Width | 16bit | |
| Address Bus Width | 14bit | |
| Number of Bits per Word | 16bit | |
| Maximum Random Access Time | 5.4ns | |
| Number of Words | 8M | |
| Mounting Type | Surface Mount | |
| Package Type | TSOP | |
| Pin Count | 54 | |
| Dimensions | 22.42 x 10.29 x 1.05mm | |
| Height | 1.05mm | |
| Length | 22.42mm | |
| Maximum Operating Supply Voltage | 3.6 V | |
| Maximum Operating Temperature | +70 °C | |
| Minimum Operating Temperature | 0 °C | |
| Minimum Operating Supply Voltage | 3 V | |
| Width | 10.29mm | |
| 選取全部 | ||
|---|---|---|
品牌 ISSI | ||
Memory Size 128Mbit | ||
Organisation 8M x 16 | ||
Data Rate 143MHz | ||
Data Bus Width 16bit | ||
Address Bus Width 14bit | ||
Number of Bits per Word 16bit | ||
Maximum Random Access Time 5.4ns | ||
Number of Words 8M | ||
Mounting Type Surface Mount | ||
Package Type TSOP | ||
Pin Count 54 | ||
Dimensions 22.42 x 10.29 x 1.05mm | ||
Height 1.05mm | ||
Length 22.42mm | ||
Maximum Operating Supply Voltage 3.6 V | ||
Maximum Operating Temperature +70 °C | ||
Minimum Operating Temperature 0 °C | ||
Minimum Operating Supply Voltage 3 V | ||
Width 10.29mm | ||
Dynamic RAM, ISSI
ISSI SDR SDRAM range offers synchronous interface with programmable CAS Latency (2/3 clocks). High speed data transfer is achieved using the pipeline process and the Synchronous DRAM SDR series offer burst read/write and burst read/single write making them ideally for use in computers applications. ISSI’s SDR SDRAM devices come in a range of different organisations and memory sizes, operating on a 3.3V power supply.
LVTTL interface
Input/output signals refer to the rising edge of the clock input
Programmable burst sequence: Sequential/Interleave; Programmable burst length
Random column address every clock cycle
Self-refresh and Auto Refresh mode
Input/output signals refer to the rising edge of the clock input
Programmable burst sequence: Sequential/Interleave; Programmable burst length
Random column address every clock cycle
Self-refresh and Auto Refresh mode