Infineon SDRAM 64 MB Surface, 24-Pin 8 bit FBGA-24 Ball
- RS庫存編號:
- 273-7513
- 製造零件編號:
- S27KL0642DPBHI020
- 製造商:
- Infineon
此圖片僅供參考，請參閲產品詳細資訊及規格
可享批量折扣
小計（1 件）*
TWD104.00
(不含稅)
TWD109.20
(含稅)
添加 13 件 件可免費送貨
有庫存
- 311 件準備從其他地點送貨
**需要更多嗎？**輸入您需要的數量，然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 |
|---|---|
| 1 - 9 | TWD104.00 |
| 10 - 24 | TWD102.00 |
| 25 - 49 | TWD100.00 |
| 50 - 99 | TWD98.00 |
| 100 + | TWD96.00 |
* 參考價格
- RS庫存編號:
- 273-7513
- 製造零件編號:
- S27KL0642DPBHI020
- 製造商:
- Infineon
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Infineon | |
| Memory Size | 64MB | |
| Product Type | SDRAM | |
| Data Bus Width | 8bit | |
| Maximum Clock Frequency | 200MHz | |
| Number of Bits per Word | 16 | |
| Mount Type | Surface | |
| Package Type | FBGA-24 Ball | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 24 | |
| Maximum Operating Temperature | 105°C | |
| Series | S27K | |
| Standards/Approvals | No | |
| Width | 8 mm | |
| Length | 6mm | |
| Height | 1mm | |
| Automotive Standard | AEC-Q100 Grade 2 & 3 | |
| Maximum Supply Voltage | 3.6V | |
| Supply Current | 360μA | |
| Minimum Supply Voltage | 1.8V | |
| 選取全部 | ||
|---|---|---|
品牌 Infineon | ||
Memory Size 64MB | ||
Product Type SDRAM | ||
Data Bus Width 8bit | ||
Maximum Clock Frequency 200MHz | ||
Number of Bits per Word 16 | ||
Mount Type Surface | ||
Package Type FBGA-24 Ball | ||
Minimum Operating Temperature -40°C | ||
Pin Count 24 | ||
Maximum Operating Temperature 105°C | ||
Series S27K | ||
Standards/Approvals No | ||
Width 8 mm | ||
Length 6mm | ||
Height 1mm | ||
Automotive Standard AEC-Q100 Grade 2 & 3 | ||
Maximum Supply Voltage 3.6V | ||
Supply Current 360μA | ||
Minimum Supply Voltage 1.8V | ||
The Infineon DRAM is a high speed CMOS, self refresh DRAM, with HYPERBUS interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS interface master. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as Pseudo Static RAM.
200 MHz maximum clock rate
Data throughput up to 400 MBps
Bidirectional read write data strobe
Automotive AEC Q100 Grade 2 and 3
Optional DDR centre aligned read strobe
DDR transfers data on both edges of the clock
相關連結
- Infineon S27KL0642DPBHI020 SDRAM 64 MB Surface, 24-Pin 8 bit FBGA-24 Ball
- Infineon DDR SDRAM Memory 64 MB Surface, 24-Pin 8 bit FBGA
- Infineon S27KS0643GABHV020 DDR SDRAM Memory 64 MB Surface, 24-Pin 8 bit FBGA
- Alliance Memory SDRAM 64 MB Surface, 54-Pin 16 bit FBGA
- Intelligent Memory IM6432SDBATG-6I SDRAM 64 MB Surface, 90-Pin 16 bit FBGA
- Intelligent Memory IM6432SDBABG-6I SDRAM 64 MB Surface, 90-Pin 16 bit FBGA
- Intelligent Memory IM6416SDBABG-6I SDRAM 64 MB Surface, 54-Pin 16 bit FBGA
- Intelligent Memory IM6416SDBATG-6I SDRAM 64 MB Surface, 54-Pin 16 bit FBGA