Infineon S27KL0642DPBHI020 SDRAM 64 MB Surface, 24-Pin 8 bit FBGA-24 Ball
- RS庫存編號:
- 273-7512
- 製造零件編號:
- S27KL0642DPBHI020
- 製造商:
- Infineon
此圖片僅供參考，請參閲產品詳細資訊及規格
享受批量購買折扣
額外添加1014件可節省TWD2,737.80
查看批量定價選項小計（1 托盤，共 338 件）*
TWD45,799.00
(不含稅)
TWD48,090.64
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2027年5月17日 發貨
**需要更多嗎？**輸入您需要的數量，然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每托盤* | 節省 |
|---|---|---|---|
| 338 - 676 | TWD135.50 | TWD45,799.00 | - |
| 1014 + | TWD132.80 | TWD44,886.40 | TWD2,737.80 |
* 參考價格
- RS庫存編號:
- 273-7512
- 製造零件編號:
- S27KL0642DPBHI020
- 製造商:
- Infineon
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Infineon | |
| Memory Size | 64MB | |
| Product Type | SDRAM | |
| Data Bus Width | 8bit | |
| Number of Bits per Word | 16 | |
| Maximum Clock Frequency | 200MHz | |
| Mount Type | Surface | |
| Package Type | FBGA-24 Ball | |
| Pin Count | 24 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 105°C | |
| Height | 1mm | |
| Series | S27K | |
| Standards/Approvals | No | |
| Width | 8mm | |
| Length | 6mm | |
| Supply Current | 360μA | |
| Automotive Standard | AEC-Q100 Grade 2 & 3 | |
| Minimum Supply Voltage | 1.8V | |
| Maximum Supply Voltage | 3.6V | |
| 選取全部 | ||
|---|---|---|
品牌 Infineon | ||
Memory Size 64MB | ||
Product Type SDRAM | ||
Data Bus Width 8bit | ||
Number of Bits per Word 16 | ||
Maximum Clock Frequency 200MHz | ||
Mount Type Surface | ||
Package Type FBGA-24 Ball | ||
Pin Count 24 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 105°C | ||
Height 1mm | ||
Series S27K | ||
Standards/Approvals No | ||
Width 8mm | ||
Length 6mm | ||
Supply Current 360μA | ||
Automotive Standard AEC-Q100 Grade 2 & 3 | ||
Minimum Supply Voltage 1.8V | ||
Maximum Supply Voltage 3.6V | ||
The Infineon DRAM is a high speed CMOS, self refresh DRAM, with HYPERBUS interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS interface master. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as Pseudo Static RAM.
200 MHz maximum clock rate
Data throughput up to 400 MBps
Bidirectional read write data strobe
Automotive AEC Q100 Grade 2 and 3
Optional DDR centre aligned read strobe
DDR transfers data on both edges of the clock
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