Alliance Memory SDRAM 512 MB Surface, 96-Pin 16 bit FBGA
- RS庫存編號:
- 230-8423
- 製造零件編號:
- AS4C32M16D3L-12BIN
- 製造商:
- Alliance Memory
此圖片僅供參考，請參閲產品詳細資訊及規格
可享批量折扣
小計（1 托盤，共 190 件）*
TWD27,493.00
(不含稅)
TWD28,868.60
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2026年5月04日 發貨
**需要更多嗎？**輸入您需要的數量，然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每托盤* |
|---|---|---|
| 190 - 190 | TWD144.70 | TWD27,493.00 |
| 380 + | TWD141.10 | TWD26,809.00 |
* 參考價格
- RS庫存編號:
- 230-8423
- 製造零件編號:
- AS4C32M16D3L-12BIN
- 製造商:
- Alliance Memory
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Alliance Memory | |
| Product Type | SDRAM | |
| Memory Size | 512MB | |
| Organisation | 32M x 16 | |
| Data Bus Width | 16bit | |
| Address Bus Width | 12bit | |
| Number of Bits per Word | 16 | |
| Maximum Clock Frequency | 800MHz | |
| Maximum Random Access Time | 20ns | |
| Mount Type | Surface | |
| Package Type | FBGA | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 96 | |
| Maximum Operating Temperature | 95°C | |
| Width | 13 mm | |
| Length | 8mm | |
| Standards/Approvals | RoHS | |
| Series | AS4C32M16D3L | |
| Height | 1mm | |
| Minimum Supply Voltage | 1.283V | |
| Maximum Supply Voltage | 1.45V | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Alliance Memory | ||
Product Type SDRAM | ||
Memory Size 512MB | ||
Organisation 32M x 16 | ||
Data Bus Width 16bit | ||
Address Bus Width 12bit | ||
Number of Bits per Word 16 | ||
Maximum Clock Frequency 800MHz | ||
Maximum Random Access Time 20ns | ||
Mount Type Surface | ||
Package Type FBGA | ||
Minimum Operating Temperature -40°C | ||
Pin Count 96 | ||
Maximum Operating Temperature 95°C | ||
Width 13 mm | ||
Length 8mm | ||
Standards/Approvals RoHS | ||
Series AS4C32M16D3L | ||
Height 1mm | ||
Minimum Supply Voltage 1.283V | ||
Maximum Supply Voltage 1.45V | ||
Automotive Standard No | ||
The Alliance Memory 512Mb Double-Data-Rate-3L (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.
8 internal banks for concurrent operation
8n-bit prefetch architecture
Pipelined internal architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
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