Winbond DDR2 SDRAM 128 MB Surface, 84-Pin 16 bit TFBGA
- RS庫存編號:
- 188-2730P
- 製造零件編號:
- W9712G6KB25I
- 製造商:
- Winbond
此圖片僅供參考，請參閲產品詳細資訊及規格
可享批量折扣
查看批量定價選項小計 55 件 (以盤裝提供)*
TWD5,313.00
(不含稅)
TWD5,578.65
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2026年10月27日 發貨
**需要更多嗎？**輸入您需要的數量，然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 |
|---|---|
| 55 - 100 | TWD96.60 |
| 105 + | TWD95.20 |
* 參考價格
- RS庫存編號:
- 188-2730P
- 製造零件編號:
- W9712G6KB25I
- 製造商:
- Winbond
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Winbond | |
| Memory Size | 128MB | |
| Product Type | DDR2 SDRAM | |
| Data Bus Width | 16bit | |
| Address Bus Width | 15bit | |
| Number of Bits per Word | 8 | |
| Maximum Random Access Time | 0.4ns | |
| Number of Words | 16M | |
| Mount Type | Surface | |
| Package Type | TFBGA | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 84 | |
| Maximum Operating Temperature | 95°C | |
| Length | 12.6mm | |
| Standards/Approvals | RoHS | |
| Series | W9712G6KB | |
| Height | 0.8mm | |
| Minimum Supply Voltage | 1.7V | |
| Maximum Supply Voltage | 1.9V | |
| Automotive Standard | No | |
| Supply Current | 135mA | |
| 選取全部 | ||
|---|---|---|
品牌 Winbond | ||
Memory Size 128MB | ||
Product Type DDR2 SDRAM | ||
Data Bus Width 16bit | ||
Address Bus Width 15bit | ||
Number of Bits per Word 8 | ||
Maximum Random Access Time 0.4ns | ||
Number of Words 16M | ||
Mount Type Surface | ||
Package Type TFBGA | ||
Minimum Operating Temperature -40°C | ||
Pin Count 84 | ||
Maximum Operating Temperature 95°C | ||
Length 12.6mm | ||
Standards/Approvals RoHS | ||
Series W9712G6KB | ||
Height 0.8mm | ||
Minimum Supply Voltage 1.7V | ||
Maximum Supply Voltage 1.9V | ||
Automotive Standard No | ||
Supply Current 135mA | ||
- COO (Country of Origin):
- TW
The W9712G6KB is a 128M bits DDR2 SDRAM and speed involving -25, 25I and -3.
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5 and 6
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and /CLK)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
Posted /CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18