Alliance Memory AS4C512M16D3LA-10BCN SDRAM 8 GB Surface, 96-Pin 16 bit FBGA-96 Ball
- RS庫存編號:
- 425-187
- 製造零件編號:
- AS4C512M16D3LA-10BCN
- 製造商:
- Alliance Memory
小計（1 托盤，共 180 件）*
TWD142,074.00
(不含稅)
TWD149,176.80
(含稅)
添加 180 件 件可免費送貨
暫時缺貨
- 從 2026年5月12日 發貨
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單位 | 每單位 | 每托盤* |
|---|---|---|
| 180 + | TWD789.30 | TWD142,074.00 |
* 參考價格
- RS庫存編號:
- 425-187
- 製造零件編號:
- AS4C512M16D3LA-10BCN
- 製造商:
- Alliance Memory
規格
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法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Alliance Memory | |
| Memory Size | 8GB | |
| Product Type | SDRAM | |
| Organisation | 512M x 16 | |
| Data Bus Width | 16bit | |
| Address Bus Width | 16bit | |
| Maximum Clock Frequency | 933MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 20ns | |
| Number of Words | 64M | |
| Mount Type | Surface | |
| Package Type | FBGA-96 Ball | |
| Pin Count | 96 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 105°C | |
| Width | 9 mm | |
| Standards/Approvals | Lead-Free (RoHS) and Halogen-Free | |
| Length | 13.5mm | |
| Height | 1.2mm | |
| Series | AS4C512M16D3LA | |
| Minimum Supply Voltage | 1.283V | |
| Maximum Supply Voltage | 1.45V | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Alliance Memory | ||
Memory Size 8GB | ||
Product Type SDRAM | ||
Organisation 512M x 16 | ||
Data Bus Width 16bit | ||
Address Bus Width 16bit | ||
Maximum Clock Frequency 933MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 20ns | ||
Number of Words 64M | ||
Mount Type Surface | ||
Package Type FBGA-96 Ball | ||
Pin Count 96 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 105°C | ||
Width 9 mm | ||
Standards/Approvals Lead-Free (RoHS) and Halogen-Free | ||
Length 13.5mm | ||
Height 1.2mm | ||
Series AS4C512M16D3LA | ||
Minimum Supply Voltage 1.283V | ||
Maximum Supply Voltage 1.45V | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Alliance Memory 8Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Write Leveling
ZQ Calibration
RoHS compliant
Auto Refresh and Self Refresh
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