Microchip AT91SAM9N12-CUR ARM926EJ-S Microprocessor SAM9N12 32 bit ARM 400 MHz 217-Pin BGA
- RS庫存編號:
- 775-389
- 製造零件編號:
- AT91SAM9N12-CUR
- 製造商:
- Microchip
N
小計（1 卷，共 500 件）*
TWD144,900.00
(不含稅)
TWD152,145.00
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2026年8月06日 發貨
**需要更多嗎？**輸入您需要的數量，然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每卷* |
|---|---|---|
| 500 + | TWD289.80 | TWD144,900.00 |
* 參考價格
- RS庫存編號:
- 775-389
- 製造零件編號:
- AT91SAM9N12-CUR
- 製造商:
- Microchip
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Microchip | |
| Product Type | Microprocessor | |
| Series | SAM9N12 | |
| Device Core | ARM926EJ-S | |
| Data Bus Width | 32bit | |
| Instruction Set Architecture | ARM | |
| Maximum Clock Frequency | 400MHz | |
| Interface Type | ADC, LCD, SPI, USART, USB | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 0.9V | |
| Package Type | BGA | |
| Maximum Supply Voltage | 1.1V | |
| Pin Count | 217 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Width | 15mm | |
| Length | 14mm | |
| Height | 1.4mm | |
| Automotive Standard | No | |
| Number of Cores | 1 | |
| 選取全部 | ||
|---|---|---|
品牌 Microchip | ||
Product Type Microprocessor | ||
Series SAM9N12 | ||
Device Core ARM926EJ-S | ||
Data Bus Width 32bit | ||
Instruction Set Architecture ARM | ||
Maximum Clock Frequency 400MHz | ||
Interface Type ADC, LCD, SPI, USART, USB | ||
Mount Type Surface | ||
Minimum Supply Voltage 0.9V | ||
Package Type BGA | ||
Maximum Supply Voltage 1.1V | ||
Pin Count 217 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Width 15mm | ||
Length 14mm | ||
Height 1.4mm | ||
Automotive Standard No | ||
Number of Cores 1 | ||
- COO (Country of Origin):
- CN
The Microchip microprocessor serves as a powerful foundation for multi-tasking applications, optimising performance and power efficiency with its Advanced architecture and integrated features.
Supports both 32-bit ARM and 16-bit Thumb instruction sets for flexible performance
Features a Memory Management Unit (MMU) for comprehensive memory control
Incorporates Harvard architecture with separate instruction and data buses for enhanced throughput
Offers tightly-coupled memory interfaces for reduced latency in critical applications
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