Microchip AT91SAM9G25-BFU-999 ARM926EJ-S Microprocessor SAM9G25 32 bit ARM 400 MHz 247-Pin VFBGA
- RS庫存編號:
- 775-376
- 製造零件編號:
- AT91SAM9G25-BFU-999
- 製造商:
- Microchip
N
小計（1 卷，共 1000 件）*
TWD316,100.00
(不含稅)
TWD331,900.00
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2026年8月21日 發貨
**需要更多嗎？**輸入您需要的數量，然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每卷* |
|---|---|---|
| 1000 + | TWD316.10 | TWD316,100.00 |
* 參考價格
- RS庫存編號:
- 775-376
- 製造零件編號:
- AT91SAM9G25-BFU-999
- 製造商:
- Microchip
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Microchip | |
| Product Type | Microprocessor | |
| Series | SAM9G25 | |
| Device Core | ARM926EJ-S | |
| Data Bus Width | 32bit | |
| Instruction Set Architecture | ARM | |
| Maximum Clock Frequency | 400MHz | |
| Interface Type | ADC, LCD, SPI, USART, USB | |
| Mount Type | Surface | |
| Package Type | VFBGA | |
| Minimum Supply Voltage | 0.9V | |
| Maximum Supply Voltage | 1.1V | |
| Pin Count | 247 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Number of Cores | 1 | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Microchip | ||
Product Type Microprocessor | ||
Series SAM9G25 | ||
Device Core ARM926EJ-S | ||
Data Bus Width 32bit | ||
Instruction Set Architecture ARM | ||
Maximum Clock Frequency 400MHz | ||
Interface Type ADC, LCD, SPI, USART, USB | ||
Mount Type Surface | ||
Package Type VFBGA | ||
Minimum Supply Voltage 0.9V | ||
Maximum Supply Voltage 1.1V | ||
Pin Count 247 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Number of Cores 1 | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Microchip versatile microprocessor is designed primarily for multi-tasking applications, featuring robust memory management capabilities alongside high performance. Its efficient execution supports both ARM and Thumb instruction sets, enhancing code density.
Supports both 32-bit ARM and 16-bit Thumb instruction sets for flexible coding
Includes a Memory Management Unit (MMU) for improved task handling and system management
Features separate instruction and data caches, optimising performance across operations
Provides tightly-coupled memory interfaces for minimal latency and enhanced speed
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