Texas Instruments DS90UB924TRHSTQ1, LVDS Serialiser/Deserialiser 4 LVCMOS LVDS, 48-Pin WQFN
- RS庫存編號:
- 268-7482
- 製造零件編號:
- DS90UB924TRHSTQ1
- 製造商:
- Texas Instruments
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- RS庫存編號:
- 268-7482
- 製造零件編號:
- DS90UB924TRHSTQ1
- 製造商:
- Texas Instruments
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Texas Instruments | |
| Number of Drivers | 4 | |
| Product Type | LVDS Serialiser/Deserialiser | |
| Input Type | LVCMOS | |
| Output Type | LVDS | |
| Transmission Data Rate | 3.36Gbps | |
| Number of Elements per Chip | 4 | |
| Mount Type | Surface | |
| Package Type | WQFN | |
| Pin Count | 48 | |
| Minimum Supply Voltage | 0.3V | |
| Differential Input High Threshold Voltage | 50mV | |
| Maximum Supply Voltage | 4V | |
| Differential Input Low Threshold Voltage | -50mV | |
| ESD Protection | Yes | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 105°C | |
| Series | DS | |
| Standards/Approvals | RoHS | |
| Height | 0.8mm | |
| Automotive Standard | AEC-Q100 | |
| 選取全部 | ||
|---|---|---|
品牌 Texas Instruments | ||
Number of Drivers 4 | ||
Product Type LVDS Serialiser/Deserialiser | ||
Input Type LVCMOS | ||
Output Type LVDS | ||
Transmission Data Rate 3.36Gbps | ||
Number of Elements per Chip 4 | ||
Mount Type Surface | ||
Package Type WQFN | ||
Pin Count 48 | ||
Minimum Supply Voltage 0.3V | ||
Differential Input High Threshold Voltage 50mV | ||
Maximum Supply Voltage 4V | ||
Differential Input Low Threshold Voltage -50mV | ||
ESD Protection Yes | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 105°C | ||
Series DS | ||
Standards/Approvals RoHS | ||
Height 0.8mm | ||
Automotive Standard AEC-Q100 | ||
The Texas Instruments Deserializer device converts a high speed serialized Interface with an embedded clock, delivered over a single signal pair to four LVDS data or control streams, one LVDS clock pair and I2S audio data. Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signalling.
DC balanced and scrambled data with
Embedded clock
Adaptive cable equalization
Internal pattern generation
Backward compatible modes
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