Nexperia 74AUP1T97GW-Q100H 3-Input Multifunction Logic Gate, 6-Pin SC-88
- RS庫存編號:
- 240-1727
- 製造零件編號:
- 74AUP1T97GW-Q100H
- 製造商:
- Nexperia
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TWD167.50
(不含稅)
TWD176.00
(含稅)
訂單超過 $1,300.00 免費送貨
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- 加上 2,900 件從 2026年11月02日 起發貨
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單位 | 每單位 | 每包* |
|---|---|---|
| 25 - 25 | TWD6.70 | TWD167.50 |
| 50 - 75 | TWD6.60 | TWD165.00 |
| 100 - 225 | TWD6.60 | TWD165.00 |
| 250 - 975 | TWD6.40 | TWD160.00 |
| 1000 + | TWD6.20 | TWD155.00 |
* 參考價格
- RS庫存編號:
- 240-1727
- 製造零件編號:
- 74AUP1T97GW-Q100H
- 製造商:
- Nexperia
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Nexperia | |
| Product Type | Logic Gate | |
| Logic Function | Multifunction | |
| Mount Type | Surface | |
| Number of Inputs per Gate | 3 | |
| Package Type | SC-88 | |
| Pin Count | 6 | |
| Logic Family | AUP | |
| Maximum Propagation Delay Time @ CL | 4.9ns | |
| Minimum Operating Temperature | -40°C | |
| Maximum High Level Output Current | -4mA | |
| Maximum Operating Temperature | 125°C | |
| Length | 2.2mm | |
| Minimum Supply Voltage | 2.3V | |
| Height | 1.1mm | |
| Maximum Supply Voltage | 3.6V | |
| Series | 74AUP1T97GW-Q100H | |
| Standards/Approvals | JEDEC | |
| Maximum Low Level Output Current | 4mA | |
| Automotive Standard | AEC-Q100 | |
| 選取全部 | ||
|---|---|---|
品牌 Nexperia | ||
Product Type Logic Gate | ||
Logic Function Multifunction | ||
Mount Type Surface | ||
Number of Inputs per Gate 3 | ||
Package Type SC-88 | ||
Pin Count 6 | ||
Logic Family AUP | ||
Maximum Propagation Delay Time @ CL 4.9ns | ||
Minimum Operating Temperature -40°C | ||
Maximum High Level Output Current -4mA | ||
Maximum Operating Temperature 125°C | ||
Length 2.2mm | ||
Minimum Supply Voltage 2.3V | ||
Height 1.1mm | ||
Maximum Supply Voltage 3.6V | ||
Series 74AUP1T97GW-Q100H | ||
Standards/Approvals JEDEC | ||
Maximum Low Level Output Current 4mA | ||
Automotive Standard AEC-Q100 | ||
The Nexperia configurable multiple function gate is with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be
Wide supply voltage range from 2.3 V to 3.6 V
CMOS low power dissipation
High noise immunity
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Latch-up performance exceeds 100 mA per JESD 78 Class II
Low static power consumption; ICC1.5 μA (maximum)
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