Nexperia HEF4011BT,652, 4 2-Input NAND Logic Gate, 14-Pin SOIC
- RS庫存編號:
- 103-8153
- 製造零件編號:
- HEF4011BT,652
- 製造商:
- Nexperia
此圖片僅供參考，請參閲產品詳細資訊及規格
可享批量折扣
小計（1 管，共 57 件）*
TWD330.60
(不含稅)
TWD347.13
(含稅)
訂單超過 $1,300.00 免費送貨
庫存資訊目前無法查詢
單位 | 每單位 | 每管* |
|---|---|---|
| 57 - 57 | TWD5.80 | TWD330.60 |
| 114 - 228 | TWD5.70 | TWD324.90 |
| 285 - 513 | TWD5.50 | TWD313.50 |
| 570 - 1083 | TWD5.40 | TWD307.80 |
| 1140 + | TWD5.30 | TWD302.10 |
* 參考價格
- RS庫存編號:
- 103-8153
- 製造零件編號:
- HEF4011BT,652
- 製造商:
- Nexperia
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Nexperia | |
| Product Type | Logic Gate | |
| Logic Function | NAND | |
| Mount Type | Surface | |
| Number of Elements | 4 | |
| Number of Inputs per Gate | 2 | |
| Schmitt Trigger Input | No | |
| Package Type | SOIC | |
| Pin Count | 14 | |
| Logic Family | 4000 | |
| Input Type | CMOS | |
| Minimum Operating Temperature | -40°C | |
| Maximum Propagation Delay Time @ CL | 35ns | |
| Maximum High Level Output Current | -3.6mA | |
| Maximum Operating Temperature | 85°C | |
| Height | 1.45mm | |
| Maximum Supply Voltage | 15V | |
| Length | 8.75mm | |
| Standards/Approvals | No | |
| Width | 4 mm | |
| Minimum Supply Voltage | 3V | |
| Maximum Low Level Output Current | 3.6mA | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Nexperia | ||
Product Type Logic Gate | ||
Logic Function NAND | ||
Mount Type Surface | ||
Number of Elements 4 | ||
Number of Inputs per Gate 2 | ||
Schmitt Trigger Input No | ||
Package Type SOIC | ||
Pin Count 14 | ||
Logic Family 4000 | ||
Input Type CMOS | ||
Minimum Operating Temperature -40°C | ||
Maximum Propagation Delay Time @ CL 35ns | ||
Maximum High Level Output Current -3.6mA | ||
Maximum Operating Temperature 85°C | ||
Height 1.45mm | ||
Maximum Supply Voltage 15V | ||
Length 8.75mm | ||
Standards/Approvals No | ||
Width 4 mm | ||
Minimum Supply Voltage 3V | ||
Maximum Low Level Output Current 3.6mA | ||
Automotive Standard No | ||
The HEF4011B is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
Key features and benefits
Mixed 5 V and 3.3 V applications
Reduce time to market for complex designs
Save board space
Open-drain output options
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant options
Low input threshold options
CMOS low power
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