Nexperia 8-Bit Octal D Type Latch, Transparent, 3 State, 20-Pin TSSOP
- RS庫存編號:
- 170-4836
- 製造零件編號:
- 74LVC573APW,118
- 製造商:
- Nexperia
此圖片僅供參考,請參閲產品詳細資訊及規格
可享批量折扣
小計(1 卷,共 2500 件)*
TWD15,000.00
(不含稅)
TWD15,750.00
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2026年9月07日 發貨
**需要更多嗎?**輸入您需要的數量,然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每卷* |
|---|---|---|
| 2500 - 2500 | TWD6.00 | TWD15,000.00 |
| 5000 + | TWD5.80 | TWD14,500.00 |
* 參考價格
- RS庫存編號:
- 170-4836
- 製造零件編號:
- 74LVC573APW,118
- 製造商:
- Nexperia
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Nexperia | |
| Product Type | Octal D Type Latch | |
| Logic Family | 74LVC | |
| Logic Function | D Type | |
| Latch Mode | Transparent | |
| Number of Bits | 8 | |
| Number of Channels | 8 | |
| Output Type | 3 State | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 1.2V | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Height | 0.95mm | |
| Standards/Approvals | No | |
| Width | 4.5 mm | |
| Length | 6.6mm | |
| Series | 74LVC | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Nexperia | ||
Product Type Octal D Type Latch | ||
Logic Family 74LVC | ||
Logic Function D Type | ||
Latch Mode Transparent | ||
Number of Bits 8 | ||
Number of Channels 8 | ||
Output Type 3 State | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Minimum Supply Voltage 1.2V | ||
Package Type TSSOP | ||
Pin Count 20 | ||
Maximum Supply Voltage 3.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Height 0.95mm | ||
Standards/Approvals No | ||
Width 4.5 mm | ||
Length 6.6mm | ||
Series 74LVC | ||
Automotive Standard No | ||
- COO (Country of Origin):
- CN
The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all internal latches. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, that is, a latch output will change each time its corresponding D-input changes.
Mixed 5 V and 3.3 V applications
Save board space
Low cost Interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Memory controllers
Backplane interfaces
相關連結
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