Nexperia 74LVC74APW,118 2 Flip Flop IC 74LVC, D Type, 14-Pin TSSOP
- RS庫存編號:
- 170-5415
- 製造零件編號:
- 74LVC74APW,118
- 製造商:
- Nexperia
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享受批量購買折扣
額外添加650件可節省TWD130.00
查看批量定價選項小計（1 包，共 50 件）*
TWD240.00
(不含稅)
TWD252.00
(含稅)
訂單超過 $1,300.00 免費送貨
有庫存
- 加上 950 件從 2026年11月16日 起發貨
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單位 | 每單位 | 每包* | 節省 |
|---|---|---|---|
| 50 - 600 | TWD4.80 | TWD240.00 | - |
| 650 - 1200 | TWD4.60 | TWD230.00 | TWD130.00 |
| 1250 + | TWD4.60 | TWD230.00 | TWD250.00 |
* 參考價格
- RS庫存編號:
- 170-5415
- 製造零件編號:
- 74LVC74APW,118
- 製造商:
- Nexperia
規格
產品概覽和技術數據資料表
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Nexperia | |
| Logic Family | 74LVC | |
| Product Type | Flip Flop IC | |
| Input Type | Single Ended | |
| Output Type | D Type | |
| Clock Frequency | 120MHz | |
| Polarity | Inverting, Non-Inverting | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 1.65V | |
| Package Type | TSSOP | |
| Pin Count | 14 | |
| Maximum Supply Voltage | 3.6V | |
| Flip-Flop Type | D Flip-Flop | |
| Trigger Type | Positive Edge | |
| Maximum Propagation Delay Time @ CL | 6.5ns | |
| Minimum Operating Temperature | -40°C | |
| Number of Elements per Chip | 2 | |
| Maximum Operating Temperature | 125°C | |
| Length | 5.1mm | |
| Height | 950μm | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Nexperia | ||
Logic Family 74LVC | ||
Product Type Flip Flop IC | ||
Input Type Single Ended | ||
Output Type D Type | ||
Clock Frequency 120MHz | ||
Polarity Inverting, Non-Inverting | ||
Mount Type Surface | ||
Minimum Supply Voltage 1.65V | ||
Package Type TSSOP | ||
Pin Count 14 | ||
Maximum Supply Voltage 3.6V | ||
Flip-Flop Type D Flip-Flop | ||
Trigger Type Positive Edge | ||
Maximum Propagation Delay Time @ CL 6.5ns | ||
Minimum Operating Temperature -40°C | ||
Number of Elements per Chip 2 | ||
Maximum Operating Temperature 125°C | ||
Length 5.1mm | ||
Height 950μm | ||
Standards/Approvals No | ||
Automotive Standard No | ||
- COO (Country of Origin):
- CN
The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous Active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
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