Nexperia 1 Flip Flop IC 74LVC, D Type, 20-Pin TSSOP
- RS庫存編號:
- 170-4863
- 製造零件編號:
- 74LVC273PW,118
- 製造商:
- Nexperia
此圖片僅供參考，請參閲產品詳細資訊及規格
可享批量折扣
小計（1 卷，共 2500 件）*
TWD22,000.00
(不含稅)
TWD23,100.00
(含稅)
訂單超過 $1,300.00 免費送貨
有庫存
- 2,500 件準備從其他地點送貨
**需要更多嗎？**輸入您需要的數量，然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每卷* |
|---|---|---|
| 2500 - 2500 | TWD8.80 | TWD22,000.00 |
| 5000 + | TWD8.50 | TWD21,250.00 |
* 參考價格
- RS庫存編號:
- 170-4863
- 製造零件編號:
- 74LVC273PW,118
- 製造商:
- Nexperia
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Nexperia | |
| Logic Family | 74LVC | |
| Product Type | Flip Flop IC | |
| Input Type | Single Ended | |
| Output Type | D Type | |
| Clock Frequency | 150MHz | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 1.65V | |
| Package Type | TSSOP | |
| Maximum Supply Voltage | 3.6V | |
| Pin Count | 20 | |
| Maximum Propagation Delay Time @ CL | 10.5ns | |
| Trigger Type | Positive Edge | |
| Flip-Flop Type | D Flip-Flop | |
| Minimum Operating Temperature | -40°C | |
| Number of Elements per Chip | 1 | |
| Maximum Operating Temperature | 125°C | |
| Length | 6.6mm | |
| Height | 0.95mm | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Nexperia | ||
Logic Family 74LVC | ||
Product Type Flip Flop IC | ||
Input Type Single Ended | ||
Output Type D Type | ||
Clock Frequency 150MHz | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Minimum Supply Voltage 1.65V | ||
Package Type TSSOP | ||
Maximum Supply Voltage 3.6V | ||
Pin Count 20 | ||
Maximum Propagation Delay Time @ CL 10.5ns | ||
Trigger Type Positive Edge | ||
Flip-Flop Type D Flip-Flop | ||
Minimum Operating Temperature -40°C | ||
Number of Elements per Chip 1 | ||
Maximum Operating Temperature 125°C | ||
Length 6.6mm | ||
Height 0.95mm | ||
Standards/Approvals No | ||
Automotive Standard No | ||
The 74LVC273 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and Master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
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