Renesas Electronics 74FCT3807PYGI PLL Clock Driver, 20-Pin 10 SSOP
- RS庫存編號:
- 263-7956
- 製造零件編號:
- 74FCT3807PYGI
- 製造商:
- Renesas Electronics
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可享批量折扣
小計（1 包，共 5 件）*
TWD216.00
(不含稅)
TWD226.80
(含稅)
訂單超過 $1,300.00 免費送貨
有庫存
- 加上 380 件從 2026年2月02日 起發貨
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單位 | 每單位 | 每包* |
|---|---|---|
| 5 - 5 | TWD43.20 | TWD216.00 |
| 10 - 20 | TWD38.60 | TWD193.00 |
| 25 - 95 | TWD36.40 | TWD182.00 |
| 100 - 250 | TWD30.80 | TWD154.00 |
| 255 + | TWD30.40 | TWD152.00 |
* 參考價格
- RS庫存編號:
- 263-7956
- 製造零件編號:
- 74FCT3807PYGI
- 製造商:
- Renesas Electronics
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Renesas Electronics | |
| Product Type | PLL Clock Driver | |
| Mount Type | Surface | |
| Package Type | SSOP | |
| Minimum Supply Voltage | -0.5V | |
| Pin Count | 20 | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | RoHS | |
| Height | 2.34mm | |
| Series | 74FCT3807A | |
| Width | 7.6 mm | |
| Length | 12.8mm | |
| Maximum Output Frequency | 133.33Hz | |
| Automotive Standard | No | |
| Number of Outputs | 10 | |
| 選取全部 | ||
|---|---|---|
品牌 Renesas Electronics | ||
Product Type PLL Clock Driver | ||
Mount Type Surface | ||
Package Type SSOP | ||
Minimum Supply Voltage -0.5V | ||
Pin Count 20 | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals RoHS | ||
Height 2.34mm | ||
Series 74FCT3807A | ||
Width 7.6 mm | ||
Length 12.8mm | ||
Maximum Output Frequency 133.33Hz | ||
Automotive Standard No | ||
Number of Outputs 10 | ||
- COO (Country of Origin):
- MY
The Renesas Electronics clock driver is built using advanced dual metal CMOS technology. This low skew clock driver offers 1:10 fan out. The large fan out from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. It offers low capacitance inputs with hysteresis for improved noise margins. Multiple power and grounds reduce noise. Typical applications are clock and signal distribution.
Guaranteed low skew < 500ps
Very low duty cycle distortion < 1.0ns
Very low CMOS power levels
TTL compatible inputs and outputs
Two independent output banks with 3-state control