Renesas Electronics 74FCT38072SDCGI PLL Clock Driver, 8-Pin 2 SOIC
- RS庫存編號:
- 263-7948
- 製造零件編號:
- 74FCT38072SDCGI
- 製造商:
- Renesas Electronics
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小計(1 包,共 5 件)*
TWD357.00
(不含稅)
TWD374.85
(含稅)
訂單超過 $1,300.00 免費送貨
有庫存
- 加上 260 件從 2026年2月02日 起發貨
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單位 | 每單位 | 每包* |
|---|---|---|
| 5 - 5 | TWD71.40 | TWD357.00 |
| 10 - 20 | TWD64.20 | TWD321.00 |
| 25 - 45 | TWD60.80 | TWD304.00 |
| 50 - 90 | TWD59.20 | TWD296.00 |
| 95 + | TWD58.20 | TWD291.00 |
* 參考價格
- RS庫存編號:
- 263-7948
- 製造零件編號:
- 74FCT38072SDCGI
- 製造商:
- Renesas Electronics
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Renesas Electronics | |
| Product Type | PLL Clock Driver | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Minimum Supply Voltage | -0.5V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Series | IDT74FCT38072 | |
| Standards/Approvals | RoHS | |
| Height | 1.75mm | |
| Width | 4 mm | |
| Length | 5mm | |
| Automotive Standard | No | |
| Number of Outputs | 2 | |
| Maximum Output Frequency | 166MHz | |
| 選取全部 | ||
|---|---|---|
品牌 Renesas Electronics | ||
Product Type PLL Clock Driver | ||
Package Type SOIC | ||
Pin Count 8 | ||
Minimum Supply Voltage -0.5V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Series IDT74FCT38072 | ||
Standards/Approvals RoHS | ||
Height 1.75mm | ||
Width 4 mm | ||
Length 5mm | ||
Automotive Standard No | ||
Number of Outputs 2 | ||
Maximum Output Frequency 166MHz | ||
The Renesas Electronics clock driver built using advanced CMOS technology. This low skew clock driver offers 1:2 fan out. The large fan out from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. Multiple power and grounds reduce noise. Typical applications are clock and signal distribution.
Advanced CMOS technology
Guaranteed low skew < 100ps
Very low duty cycle distortion< 350ps
High speed propagation delay< 3ns
Very low CMOS power levels
TTL compatible inputs and outputs
