Renesas Electronics 85102AGILF Clock Buffer, 16-Pin 7 TSSOP
- RS庫存編號:
- 216-6208
- 製造零件編號:
- 85102AGILF
- 製造商:
- Renesas Electronics
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TWD447.00
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TWD469.35
(含稅)
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- RS庫存編號:
- 216-6208
- 製造零件編號:
- 85102AGILF
- 製造商:
- Renesas Electronics
規格
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Minimum Supply Voltage | 3V | |
| Pin Count | 16 | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Series | 85102A | |
| Width | 4.4 mm | |
| Length | 5mm | |
| Height | 1mm | |
| Standards/Approvals | No | |
| Maximum Output Frequency | 200MHz | |
| Automotive Standard | No | |
| Number of Outputs | 7 | |
| 選取全部 | ||
|---|---|---|
品牌 Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Minimum Supply Voltage 3V | ||
Pin Count 16 | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Series 85102A | ||
Width 4.4 mm | ||
Length 5mm | ||
Height 1mm | ||
Standards/Approvals No | ||
Maximum Output Frequency 200MHz | ||
Automotive Standard No | ||
Number of Outputs 7 | ||
The Renesas Electronics 85102I is a low skew, high performance 1-to-2 Differential-to-HCSL fanout buffer. The 85102I has a differential clock input. The CLK0, nCLK0 input pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/ deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85102I ideal for those applications demanding well defi ned performance and repeatability.
Two 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 65ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)