Renesas Electronics 2305A-1DCG8 Clock Buffer 8-Pin SOIC

The Renesas Electronics high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133 MHz.

Phase-lock loop clock distribution
Distributes one clock input to one bank of five outputs
Power down mode
Available in SOIC package

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