Nexperia 74AUP1T08GW-Q100H 2-Input AND Schmitt Trigger Input Logic Gate, 5-Pin TSSOP-5
- RS庫存編號:
- 240-1725
- 製造零件編號:
- 74AUP1T08GW-Q100H
- 製造商:
- Nexperia
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可享批量折扣
小計（1 包，共 25 件）*
TWD165.00
(不含稅)
TWD173.25
(含稅)
訂單超過 $1,300.00 免費送貨
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- 2,975 件從 2026年6月03日 起裝運發貨
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單位 | 每單位 | 每包* |
|---|---|---|
| 25 - 25 | TWD6.60 | TWD165.00 |
| 50 - 75 | TWD6.50 | TWD162.50 |
| 100 - 225 | TWD6.40 | TWD160.00 |
| 250 - 975 | TWD6.30 | TWD157.50 |
| 1000 + | TWD6.20 | TWD155.00 |
* 參考價格
- RS庫存編號:
- 240-1725
- 製造零件編號:
- 74AUP1T08GW-Q100H
- 製造商:
- Nexperia
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Nexperia | |
| Product Type | Logic Gate | |
| Logic Function | AND | |
| Mount Type | Surface | |
| Number of Inputs per Gate | 2 | |
| Schmitt Trigger Input | Yes | |
| Package Type | TSSOP-5 | |
| Pin Count | 5 | |
| Logic Family | AUP | |
| Minimum Operating Temperature | -40°C | |
| Maximum Propagation Delay Time @ CL | 4.8ns | |
| Maximum High Level Output Current | -4mA | |
| Maximum Operating Temperature | 125°C | |
| Standards/Approvals | No | |
| Maximum Supply Voltage | 3.6V | |
| Height | 1.1mm | |
| Length | 2.25mm | |
| Minimum Supply Voltage | 2.3V | |
| Maximum Low Level Output Current | 4mA | |
| Automotive Standard | AEC-Q100 | |
| 選取全部 | ||
|---|---|---|
品牌 Nexperia | ||
Product Type Logic Gate | ||
Logic Function AND | ||
Mount Type Surface | ||
Number of Inputs per Gate 2 | ||
Schmitt Trigger Input Yes | ||
Package Type TSSOP-5 | ||
Pin Count 5 | ||
Logic Family AUP | ||
Minimum Operating Temperature -40°C | ||
Maximum Propagation Delay Time @ CL 4.8ns | ||
Maximum High Level Output Current -4mA | ||
Maximum Operating Temperature 125°C | ||
Standards/Approvals No | ||
Maximum Supply Voltage 3.6V | ||
Height 1.1mm | ||
Length 2.25mm | ||
Minimum Supply Voltage 2.3V | ||
Maximum Low Level Output Current 4mA | ||
Automotive Standard AEC-Q100 | ||
The Nexperia low-power 2 input AND gate with voltage-level translator provides the single 2-input AND function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. It is designed for logic-l
Low static power consumption; ICC1.5 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
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