Lattice FPGA ICE40HX4K-TQ144, iCE40 HX 3520 Cells, 80kbit, 440 Blocks, 144-Pin TQFP
- RS庫存編號:
- 168-4222
- 製造零件編號:
- ICE40HX4K-TQ144
- 製造商:
- Lattice Semiconductor
此圖片僅供參考,請參閲產品詳細資訊及規格
可享批量折扣
小計(1 托盤,共 60 件)*
TWD20,562.00
(不含稅)
TWD21,590.40
(含稅)
訂單超過 $1,300.00 免費送貨
有庫存
- 420 件準備從其他地點送貨
**需要更多嗎?**輸入您需要的數量,然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每托盤* |
|---|---|---|
| 60 - 240 | TWD342.70 | TWD20,562.00 |
| 300 + | TWD325.50 | TWD19,530.00 |
* 參考價格
- RS庫存編號:
- 168-4222
- 製造零件編號:
- ICE40HX4K-TQ144
- 製造商:
- Lattice Semiconductor
規格
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
透過選取一個或多個屬性來查找類似產品。
選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Lattice Semiconductor | |
| Family Name | iCE40 HX | |
| Number of Logic Cells | 3520 | |
| Number of Logic Units | 440 | |
| Number of Registers | 3520 | |
| Mounting Type | Surface Mount | |
| Package Type | TQFP | |
| Pin Count | 144 | |
| Number of RAM Bits | 80kbit | |
| Dimensions | 20 x 20 x 1.45mm | |
| Height | 1.45mm | |
| Length | 20mm | |
| Minimum Operating Temperature | -40 °C | |
| Minimum Operating Supply Voltage | 1.14 V | |
| Maximum Operating Supply Voltage | 1.26 V | |
| Maximum Operating Temperature | +85 °C | |
| Width | 20mm | |
| 選取全部 | ||
|---|---|---|
品牌 Lattice Semiconductor | ||
Family Name iCE40 HX | ||
Number of Logic Cells 3520 | ||
Number of Logic Units 440 | ||
Number of Registers 3520 | ||
Mounting Type Surface Mount | ||
Package Type TQFP | ||
Pin Count 144 | ||
Number of RAM Bits 80kbit | ||
Dimensions 20 x 20 x 1.45mm | ||
Height 1.45mm | ||
Length 20mm | ||
Minimum Operating Temperature -40 °C | ||
Minimum Operating Supply Voltage 1.14 V | ||
Maximum Operating Supply Voltage 1.26 V | ||
Maximum Operating Temperature +85 °C | ||
Width 20mm | ||
- COO (Country of Origin):
- KR
Field Programmable Gate Arrays, Lattice Semiconductor
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
An FPGA is a semiconductor device consisting of a matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. The user determines these interconnections by programming SRAM. A CLB can be simple (AND, OR gates, etc) or complex (a block of RAM). The FPGA allows changes to be made to a design even after the device is soldered into a PCB.
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