Microchip KSZ8895FQXIA, Ethernet Switch IC, 3.3 V 100 Mbps SPI, MII, I2C, SMI, SNI, MDIO, RMII, MDC, 128-Pin 3.3 V PQFP
- RS庫存編號:
- 177-3830
- 製造零件編號:
- KSZ8895FQXIA
- 製造商:
- Microchip
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TWD521.00
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- RS庫存編號:
- 177-3830
- 製造零件編號:
- KSZ8895FQXIA
- 製造商:
- Microchip
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Microchip | |
| Maximum Data Rate | 100Mbps | |
| Product Type | Ethernet Switch IC | |
| Sub Type | Switch | |
| Number of Transceivers | 5 | |
| Loopback Mode | Remote Diagnostic of Failure, PHY | |
| Standard Supported | IGMP, IEEE 802.1Q, IEEE 802.3u, IEEE | |
| Interface Type | SPI, MII, I2C, SMI, SNI, MDIO, RMII, MDC | |
| Mount Type | Surface | |
| Package Type | PQFP | |
| Maximum Supply Voltage | 3.3V | |
| Pin Count | 128 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Length | 20mm | |
| Standards/Approvals | Lead-Free | |
| Height | 3.4mm | |
| Minimum Supply Voltage | 3.3V | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Microchip | ||
Maximum Data Rate 100Mbps | ||
Product Type Ethernet Switch IC | ||
Sub Type Switch | ||
Number of Transceivers 5 | ||
Loopback Mode Remote Diagnostic of Failure, PHY | ||
Standard Supported IGMP, IEEE 802.1Q, IEEE 802.3u, IEEE | ||
Interface Type SPI, MII, I2C, SMI, SNI, MDIO, RMII, MDC | ||
Mount Type Surface | ||
Package Type PQFP | ||
Maximum Supply Voltage 3.3V | ||
Pin Count 128 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Length 20mm | ||
Standards/Approvals Lead-Free | ||
Height 3.4mm | ||
Minimum Supply Voltage 3.3V | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The KSZ8895MQX/RQX/FQX/ML is a highly-integrated, Layer 2 managed, five-port switch with numerous features designed to reduce system cost.
Advanced Switch Features
VLAN support for up to 128 active VLAN groups (full-range 4096 of VLAN IDs)
Static MAC table supports up to 32 entries
VLAN ID tag/untag options, per port basis
Comprehensive Configuration Register Access
Serial management interface (MDC/MDIO) to all PHYs registers and SMI interface (MDC/MDIO) to all registers
High-speed SPI (up to 25MHz) and I2C master Interface to all internal registers
I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode
QoS/CoS Packet Prioritization Support
Per port, 802.1p and DiffServ-based
1/2/4-queue QoS prioritization selection
Programmable weighted fair queuing for ratio control
Integrated 5-Port 10/100 Ethernet Switch
New generation switch with five MACs and five PHYs
PHYs designed with patented enhanced mixed-signal technology
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