Renesas Electronics High Performance Clock Buffer 24-Pin TSSOP
- RS庫存編號:
- 254-4946
- 製造零件編號:
- 5V2310PGGI
- 製造商:
- Renesas Electronics
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(含稅)
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單位 | 每單位 | 每管* |
|---|---|---|
| 62 - 62 | TWD115.80 | TWD7,179.60 |
| 124 - 186 | TWD113.50 | TWD7,037.00 |
| 248 - 496 | TWD111.20 | TWD6,894.40 |
| 558 + | TWD109.00 | TWD6,758.00 |
* 參考價格
- RS庫存編號:
- 254-4946
- 製造零件編號:
- 5V2310PGGI
- 製造商:
- Renesas Electronics
規格
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Renesas Electronics | |
| Product Type | High Performance Clock Buffer | |
| Maximum Input Frequency | 200MHz | |
| Mount Type | Surface | |
| Maximum Propagation Delay Time | 2.8ns | |
| Package Type | TSSOP | |
| Pin Count | 24 | |
| Number of Outputs | 10 | |
| Minimum Supply Voltage | 2.3V | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | RoHS | |
| Series | IDT5V2310 | |
| Automotive Standard | No | |
| 選取全部 | ||
|---|---|---|
品牌 Renesas Electronics | ||
Product Type High Performance Clock Buffer | ||
Maximum Input Frequency 200MHz | ||
Mount Type Surface | ||
Maximum Propagation Delay Time 2.8ns | ||
Package Type TSSOP | ||
Pin Count 24 | ||
Number of Outputs 10 | ||
Minimum Supply Voltage 2.3V | ||
Maximum Supply Voltage 3.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals RoHS | ||
Series IDT5V2310 | ||
Automotive Standard No | ||
The Renesas Electronics high performance, low skew clock buffer that operates up to 200MHz. Two banks of five outputs each provide low skew copies of CLK. Through the use of control pins 1G and 2G, the outputs of banks 1Y(0:4) and 2Y(0:4) can be placed in a low state regardless of CLK input. The device operates in 2.5V and 3.3V environments. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals. The IDT5V2310 is characterized for operation from -40°C to +85°C.
High performance 1:10 clock driver for general purpose applications
Pin-to-pin skew < 100 ps
VDD range is 2.3 V to 3.6 V
Output enable glitch suppression
Distributes one clock input to two banks of five outputs
25 Ω on-chip series dampening resistors
Available in TSSOP package
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