The 74HC74D is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of theCLOCK pulse. CLEAR and PRESET are independent of the CLOCK and are accomplished by setting the appropriate input to an "L" level. All inputs are equipped with protection circuits against static discharge or transient excess voltage
High speed: fMAX = 77 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 2.0 μA (max) at Ta = 25 Balanced propagation delays: tPLH ≈ tPHL Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V
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