Renesas Electronics RC32504A000GNK#BB0, Frequency Synthesizer 8 24-Pin 24-QFN
- RS庫存編號:
- 230-6593
- 製造零件編號:
- RC32504A000GNK#BB0
- 製造商:
- Renesas Electronics
可享批量折扣
小計(1 托盤,共 490 件)*
TWD192,668.00
(不含稅)
TWD202,301.40
(含稅)
訂單超過 $1,300.00 免費送貨
暫時缺貨
- 從 2026年2月17日 發貨
**需要更多嗎?**輸入您需要的數量,然後按一下「查看送貨日期」以查詢更多庫存和送貨詳細資訊。
單位 | 每單位 | 每托盤* |
|---|---|---|
| 490 - 1960 | TWD393.20 | TWD192,668.00 |
| 2450 + | TWD385.30 | TWD188,797.00 |
* 參考價格
- RS庫存編號:
- 230-6593
- 製造零件編號:
- RC32504A000GNK#BB0
- 製造商:
- Renesas Electronics
規格
產品概覽和技術數據資料表
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產品詳細資訊
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選取全部 | 屬性 | 值 |
|---|---|---|
| 品牌 | Renesas Electronics | |
| Conversion Rate | 20Gsps | |
| Maximum Output Frequency | 180MHz | |
| Number of Elements per Chip | 8 | |
| Mounting Type | Surface Mount | |
| Package Type | 24-QFN | |
| Pin Count | 24 | |
| 選取全部 | ||
|---|---|---|
品牌 Renesas Electronics | ||
Conversion Rate 20Gsps | ||
Maximum Output Frequency 180MHz | ||
Number of Elements per Chip 8 | ||
Mounting Type Surface Mount | ||
Package Type 24-QFN | ||
Pin Count 24 | ||
The Renesas Electronics RC32504A universal frequency translator is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs. It can act as a frequency synthesizer to locally generate the reference clock, a jitter attenuator to perform local clean-up and/or frequency translation of a centrally-supplied reference, a Synchronous Ethernet equipment clock to perform passband filtering and clean-up of network-supplied references or as a DCO for frequency margining or OTN clock applications.
Jitter below 100fs RMS (10kHz to 20MHz)
Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC)
PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)
Programmable input buffer supports HCSL, LVDS, or two LVCMOS with no external terminations needed
Reference monitor qualifies/disqualifies input clock
Programmable status output
Supports up to 1MHz I2C or up to 20MHz SPI serial processor port
Can configure itself automatically after reset through internal customer-definable One-Time Programmable (OTP) memory with up to four different configurations
4 x 4 mm 24-QFN package
4 differential/8 LVCMOS outputs
Output Enable input with programmable effect
Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC)
PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)
Programmable input buffer supports HCSL, LVDS, or two LVCMOS with no external terminations needed
Reference monitor qualifies/disqualifies input clock
Programmable status output
Supports up to 1MHz I2C or up to 20MHz SPI serial processor port
Can configure itself automatically after reset through internal customer-definable One-Time Programmable (OTP) memory with up to four different configurations
4 x 4 mm 24-QFN package
4 differential/8 LVCMOS outputs
Output Enable input with programmable effect
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
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