- RS庫存編號:
- 216-6210P
- 製造零件編號:
- 85104AGILF
- 製造商:
- Renesas Electronics
222 現貨庫存,可於6工作日發貨。
已增加
單價(不含稅) 個 (以每管裝提供)
TWD650.00
(不含稅)
TWD682.50
(含稅)
單位 | Per unit |
19 - 36 | TWD650.00 |
37 + | TWD641.00 |
- RS庫存編號:
- 216-6210P
- 製造零件編號:
- 85104AGILF
- 製造商:
- Renesas Electronics
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
The Renesas Electronics 85104I is a low skew, high performance 1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer. The 85104I has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
Four 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 100ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)
Additive phase jitter, RMS: 0.22ps (typical)
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 100ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)
Additive phase jitter, RMS: 0.22ps (typical)
For products that are Customized and under Non-cancellable & Non-returnable, Sales & Conditions apply.