- RS庫存編號:
- 216-6208P
- 製造零件編號:
- 85102AGILF
- 製造商:
- Renesas Electronics
96 現貨庫存,可於6工作日發貨。
已增加
單價(不含稅) 個 (以每管裝提供)
TWD508.00
(不含稅)
TWD533.40
(含稅)
單位 | Per unit |
24 - 47 | TWD508.00 |
48 + | TWD500.00 |
- RS庫存編號:
- 216-6208P
- 製造零件編號:
- 85102AGILF
- 製造商:
- Renesas Electronics
產品概覽和技術數據資料表
法例與合規
產品詳細資訊
The Renesas Electronics 85102I is a low skew, high performance 1-to-2 Differential-to-HCSL fanout buffer. The 85102I has a differential clock input. The CLK0, nCLK0 input pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/ deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85102I ideal for those applications demanding well defi ned performance and repeatability.
Two 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 65ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 65ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)
For products that are Customized and under Non-cancellable & Non-returnable, Sales & Conditions apply.
規格
屬性 | 值 |
---|---|
Logic Function | Clock Buffer |
Number of Clock Inputs | 5 |
Package Type | TSSOP |
Pin Count | 16 |