Cypress Semiconductor, CY2308SXI-1H

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產品詳細資訊

The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL that locks to an input clock presented on the REF pin. The PLL feedback is driven from external FBK pin, so user has flexibility to choose any one of the outputs as feedback input and connect it to FBK pin. The input-to-output skew is less than 250 ps and output-to-output skew is less than 200 ps. The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for chip and system testing purposes by the select inputs. The CY2308 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off resulting in less than 25 μA of current draw.

規格
屬性
Number of Elements per Chip 1
Maximum Supply Current 70 mA
Maximum Input Frequency 133.3MHz
Mounting Type Surface Mount
Package Type SOIC
Pin Count 16
Dimensions 9.98 x 3.98 x 1.47mm
Length 9.98mm
Width 3.98mm
Height 1.47mm
Maximum Operating Supply Voltage 3.6 V
Maximum Operating Temperature +85 °C
Maximum Output Frequency 133.3MHz
Minimum Operating Supply Voltage 3 V
Minimum Operating Temperature -40 °C
Minimum Output Frequency 10MHz
48 現貨庫存,可於6工作日發貨。
單價(不含稅) 毎管:48 個
TWD 232.60
(不含稅)
TWD 244.20
(含稅)
單位
Per unit
Per Tube*
48 - 48
TWD232.60
TWD11,164.80
96 - 96
TWD222.10
TWD10,660.80
144 - 240
TWD209.50
TWD10,056.00
288 - 480
TWD193.50
TWD9,288.00
528 +
TWD168.70
TWD8,097.60
* 參考價格